Foreword:

This column aims to record high-frequency pen interview hand-torn code questions for digital front-end autumn recruits. All articles in this column provide principle analysis, codes and waveforms, and all codes have been verified by myself.

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Table of contents

topic description

Use HDL to realize pulse density modulation (PDM), that is, according to the input 12bit pdm_in, output square waves with different duty ratios according to the following requirements:

① When pdm_in>10, pdm_out means the output waveform duty cycle is 4/pdm_in;

② When pdm_in<=10, pdm_out does not flip and output a fixed value.

Its input and output interfaces are:

input clk；
input [11:0]pdm_in；
input reset；
output pdm_out;

Solutions

Pulse Density Modulation (PDM) changes the pulse density by adjusting the duty cycle of the waveform. The ratio obtained by dividing the time T_hign when the signal logic is high by the period T_cycle is called the duty cycle.

To achieve the first requirement, when pdm_in>10, the new signal can be high in 4 clk cycles and low in (pdm_in-4) clk cycles, thus realizing a pdm_in frequency division with a duty cycle of 4 /pdm_in.

The second requirement is that when pdm_in<=10, pdm_out will not let him flip, and let the counter that realizes the frequency division be cleared.

the code

module pdm(
    input           clk     ,
    input   [11:0]  pdm_in  ,
    input           reset   ,
    output          pdm_out
);

reg pdm_processed;
reg [11:0] count;

always @(posedge clk)begin
    if(reset)begin
        pdm_processed <= 1'd0;
    end
    else if(pdm_in > 10)begin
        if(count <= 3)
            pdm_processed <= 1'b1;
        else if(count < pdm_in -1)
            pdm_processed <= 1'b0;
        else if(count == pdm_in-1)
            pdm_processed <= 1'b0;
    end
    else begin // pdm_in <= 10
        pdm_processed <= pdm_processed;  //stay 
    end
end

always @(posedge clk)begin
    if(reset)begin
        count <= 12'd0;
    end
    else begin
        if(pdm_in > 10 && count < pdm_in-1)begin
            count <= count + 1'b1;
        end
        else if(pdm_in > 10 && count == pdm_in-1)begin  // one pdm_out cycle finish
            count <= 12'd0;  
        end
        else begin // pdm_in <= 10
            count <= 12'd0;
        end
    end
end

assign pdm_out = pdm_processed;

endmodule

testbench

module pdm_tb();

reg clk,reset;
wire pdm_out;

always #5 clk = ~clk;
reg [11:0] pdm_in;

initial begin
    clk     <=  1'b0;
    reset   <=  1'b1;
    pdm_in  <=  12'd0;
    #20
    reset   <=  1'b0;
    #20
    pdm_in  <=  12'd20;
    #400
    pdm_in  <=  12'd12;
    #240
    pdm_in  <=  12'd5;
    #50
    pdm_in  <=  12'd12;
    #30
    pdm_in  <=  12'd5;
    #200
    $finish();
end

//dump fsdb 
initial begin 
    $fsdbDumpfile("pdm.fsdb");
    $fsdbDumpvars(0);
end 

pdm u_pdm(
    .clk    (clk)   ,
    .pdm_in (pdm_in),
    .reset  (reset) ,
    .pdm_out(pdm_out)
);

endmodule

output waveform

It can be seen from the waveform that we set pdm_in = 20, pdm_out is as we think, and the output is a square wave with a duty ratio of 4/20. When setting pdm_in = 12, the pdm_out output is a square wave with a duty cycle of 4/12. When setting pdm_in < 10, dpm_out remains unchanged.

For more hand-tearing code questions, you can go to the digital IC hand-tearing code--question bank

Digital IC hand tearing code-XX company written test questions (pulse density modulation)

topic description

Solutions

the code

testbench

output waveform

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