Encoding the number system
Commonly used BCD code
- 8421 yards. It is a right to code.
- More than 3 yards. It is a no right code.
- 2421 yards. Is a right to code. Characterized> 4 = 5 binary number highest bit is 1, <5 most significant bit is zero. The 5 → 1011 rather than 0101.
8-bit ASCII encoding binary code, the leftmost bit is 0.
2B or from the main memory word 4B composition in the same main memory word , the store may be in accordance with the low byte first, high byte stored after sequentially (i.e. from high byte to low byte order) storing contents of the string (also known as the little-endian mode), but also in accordance with the previously stored high byte, the lower byte is stored sequentially stored contents of the string (also known as big-endian mode).
Usually by some kind of encoding many codewords, the number of bits vary between a minimum of two arbitrary legal codewords, referred to as a check code from the code. A code from check code data is not less than 2, the error detection capability has started. Distance larger code, error detection, error correction capability of the stronger, and error detection capability is always greater than or equal the error correction capability.
Parity-check codes: in the original encoding plus a parity bit so that the overall number of check code of "1" for odd / even. , Parity-check code data can only be found in the case of an odd bit errors, but can not correct the error, the data used in the inspection of the inspection or the memory data transmission.
Hamming check code: Let n be the number of bits of useful information, the number of bits k parity bits, the information bits and parity bits n k should satisfy: n + k <= 2 k -. 1
Information bit is set D . 4 D . 3 D 2 D . 1 , 4 bits, parity bit P . 3 P 2 P . 1 , the corresponding Hamming code H . 7 H . 6 H . 5 H . 4 H . 3 H 2 H . 1 . Predetermined parity bit P I in Hamming No. 2 I. 1- position, the other bits of information bits, Hamming code for your distributed as follows:
The H 7 the H 6 the H 5 the H 4 the H 3 the H 2 the H 1
D4 D3 D2 P3 D1 P2 P1
Hamming parity bits are the data bits of each number is equal to the parity bit Hamming parity bit number of the data bits and. Parity bit P I value of all the bits from the data bits of the divergent parity bit or parity.
Using each parity check bit groups he was involved in the formation of information bits and parity bits of the parity check,
S1 = P1 ⊕ D1 ⊕ D2 ⊕ D4，
S2 = P2 ⊕ D1 ⊕ D3 ⊕ D4，
S 3 = P 3 ⊕ D 2 ⊕ D 3 ⊕ D 4
When S . 3 S 2 S . 1 is "000", then the error-free; otherwise any error, and this number is the number of bits in error, such as S . 3 S 2 S . 1 = 001, described the first error, i.e., H 1 error, the bit is inverted directly achieve the purpose of error correction.
Cyclic Redundancy Check (CRC) code
The basic idea of CRC is: K-bit information code after splicing R bit checksum, encoding the entire length of N bits, so this is also known as the code (N, K) code. In the K-bit binary information bit transmission code R left side, to be transmitted, it will be the generator polynomial G (x) modulo 2 division did (loaned bits), R generates a check code, and attached to the message, form a new binary code (CRC code), a total of K + R bits. If G (X) = X . 3 + X 2 +. 1, 1101 of the modulo 2 addition.
The receiver receives the CRC for the C . 9 C . 8 C . 7 C . 6 C . 5 C . 4 C . 3 C 2 C . 1 , made modulo 2 division by the generator polynomial G (x), if the remainder is 0, the code word error-free. If the remainder is 010, then the C 2 error.
CRC can correct one or more errors ((X) determined by a polynomial G), the actual transmission method may be selected correction (retransmission request, delete data, self-correcting, etc.) as required.
Fixed-point representation of the operational
| Encoding | Minimum coding | Minimum | Maximum coding | Maximum | Value range |
| Unsigned fixed-point integer | 0000...000 | 0 | 1111...111 | 2 N + 1 -1 | 0 ≤ x ≤ 2n+1-1 |
| Unsigned fixed-point decimal | 0.00...000 | 0 | 0.11...111 | 1-2-n | 0 ≤ x ≤ 1-2-n |
| Original code fixed-point integer | 1111...111 | -2 N +1 |
0111...111 | 2 N -1 | -2 N +1 ≤ X ≤ 2 N -1 |
| The original fixed-point decimal code | 1.111...111 | -1+2-n | 0.111...111 | 1-2-n | -1+2-n ≤ x ≤ 1-2-n |
| Complement fixed-point integer | 1000...000 | -2 N | 0111...111 | 2 N -1 | -2 N ≤ X ≤ 2 N -1 |
| Complement fixed-point decimal | 1.000...000 | -1 | 0.111...111 | 1-2-n | -1 ≤ x ≤ 1-2-n |
| Anti code fixed-point integer | 1000...000 | -2 N +1 | 0111...111 | 2 N -1 | -2 N +1 ≤ X ≤ 2 N -1 |
| Anti code fixed-point decimal | 1.000...000 | -1+2-n | 0.111...111 | 1-2-n | -1+2-n ≤ x ≤ 1-2-n |
| Frameshift fixed-point integer | 0000...000 | -2 N | 1111...111 | 2 N -1 | -2 N ≤ X ≤ 2 N -1 |
| Frameshift fixed-point decimal | No definition of fractional shift | ||||
A positive number of the original code, anti-code and complement are the same.
Original code twos complement (negative): In addition to the sign bit, from the lowest-order bit, the first one encountered before everybody remains unchanged, after you negated. (Or in addition to the sign bit, it negated, end + 1)
Known [Y] Complement seeking [-Y] up , together with the negated sign bit, last bit + 1.
n + a true value Negative complement -2 = n- + true value sign bit is removed.
Frameshift large true value is large, small frameshift true value is small.
| Code system | Fill Code | |
| positive number | The original code, anti-code complement | 0 |
| negative number | Original code | 0 |
| Complement | Tim left 0 | |
| Right Tim 1 | ||
| Inverted | 1 |
Logical shift either left or right, all add 0.
Divided into cyclic shift flag CF cyclic shift (large loop) without carry flag cyclic shift (small cycles), the process as shown:
The main features of cyclic shift is removed and data is shifted into the data, and whether the Carry depends on whether the carry flag to join the cyclic shift. For example, Rotate left with carry the data bit is to the left through the Carry flag with the maximum displacement data into the carry flag CF2, and the carry flag is shifted into the least significant bit of data.
Suitable cyclic shift data low byte and high byte data interchange.
Original code fixed-point addition and subtraction operations:
Addition rules: First the sign bit determination, if the same, the absolute values. The results of the sign bit unchanged; if different. The subtraction, the absolute value of a large number of small absolute value is subtracted, the result sign bit with a larger absolute number of the same.
Subtraction rule: the original two subtraction code number represented by first inverting the sign of the subtrahend and minuend and subtrahend after inverting the sign of the original code adding operation performed.
Note that when the machine word operation, when an overflow occurs on the left, the overflow bit lost.
Complement fixed-point addition and subtraction operations:
Sign bit in the same bit values involved in computing rules together, into the sign bit is generated to be lost, the sign bit of the result obtained by the calculation.
The results also complement arithmetic of complement.
Sign extension (refer shift rules)
Arithmetic operations in the computer, it is sometimes necessary to use a given number indicates the number of conversion into a form of a representation having a different number of bits. For example, a program need to be an 8-bit 32-bit numbers and another, in order to obtain correct results, before the 8-digit and 32-bit numbers, 8 bits must be converted into 32-bit form this is called "sign extension."
Positive sign extension: the original form of the sign bit of the symbol bit moves to new forms, new forms of showing all the additional bits are filled with zeros.
The method of the negative sign extension according to the number of different machines. Original code symbols representing negative numbers in the positive spreading the same number, but this time the sign bit is 1. Complement representation of negative numbers in sign-extended: the original form of the sign bit of the symbol bit moves to new forms, new additional bit represents all forms 1 are used (for integer) or 0 (for decimal) is filled. Anti-code representation of negative numbers in sign-extended: the original form of the sign bit of the symbol bit moves to new forms, new forms of showing all the additional bits are used to fill 1.
| Multiplication type | Sign bit | The accumulated number | Displacement | ||||
| Involved in computing | Partial product | multiplier | direction | frequency | 每位次数 | ||
| 原码一位乘法 | 否 | 2位 | 0位 | n | 右 | n | 1 |
| 补码一位乘法 | 是 | 2位 | 1位 | n + 1 | 右 | n | 1 |
| 乘法类型 | 符号位参与运算 | 加减次数 | 移位 | 说明 | |
| 方向 | 次数 | ||||
| 原码加减交替法 | 否 | N + 1 或 N + 2 | 左 | N | 若最终余数为负，需恢复余数 |
| 补码加减交替法 | 是 | N + 1 | 左 | N | 商末尾恒置 1 |
在计算机系统中，数值一律用补码来表示和存储。
强制类型转换
当大字长变量向小字长变量强制类型转换时，系统把多余的高位字节部分直接截断，低位直接赋值。
短字长到长字长变量的转换，不仅要使相应的位值相等，高位部分还会扩展为原数字的符号位。
例：short x = -4321; int y = x; unsigned short u = (unsigned short) x; unsigned int v = u;
结果：x = -4321, y = -4321, u = 61215, v = 61215
x、y、u、v 的十六进制表示分别是 0xef1f、0xffffef1f、0xef1f、0x0000ef1f
| 类型 | 16位机器 | 32位机器 | 64位机器 |
| char | 8 | 8 | 8 |
| short | 16 | 16 | 16 |
| int | 16 | 32 | 32 |
| long | 32 | 32 | 64 |
| long long | 64 | 64 | 64 |
| float | 16 | 32 | 32 |
| double | 64 | 64 | 64 |
数据按边界对齐指变量的起始地址必须能够被自身的数据类型的大小整除。
对真值 0 表示形式唯一的机器数是补码和移码。
使用补码表示时，若符号位相同，则数值位越大，码值越大。
不带进位位的循环左移将最高位进入最低位和标志寄存器 C 位。
8421码是十进制数的编码。
存储模4补码（变形补码，双符号位）仅需一个符号位，因为正确的数值两个符号位相同，只在 ALU 中采用双符号位。
在计算机中，通常用无符号数来表示主存地址。
浮点数的表示与运算
左规：当浮点数运算的结果为非规格化时要进行规格化处理，将尾数算术左移一位，阶码减1（基数为2时）的方法称为左规，左规可能要进行多次。
右规：当浮点数运算的结果尾数出现溢出（双符号位为 01 或 10）时，将尾数算术右移一位，阶码加 1（基数为2时）的方法称为右规。需要右规时，只需进行一次。
（1）原码规格化后。
正数为 0.1xx...x的形式，其最大值表示为 0.11...1，最小值表示为 0.10...0。
尾数的表示范围为 1/2 ≤ M ≤ （1-2-n）
负数为 1.1xx...x的形式，其最大值表示为 1.10...0，最小值表示为 1.11...1。
尾数的表示范围为 -（1-2-n） ≤ M ≤ -1/2。
（2）补码规格化后
正数为 0.1xx...x的形式，其最大值表示为 0.11...1，最小值表示为 0.10...0。
尾数的表示范围为 1/2 ≤ M ≤ （1-2-n）
负数为 1.0xx...x的形式，其最大值表示为 1.01...1，最小值表示为 1.0...0。
尾数的表示范围为 -1 ≤ M ≤ -（1-2-n）。
补码规格化数的尾数最高为一定与尾数符号位相反。
运算结果大于最大正数时称为正上溢，小于绝对值最大负数时称为负上溢，正上溢和负上溢统称为上溢。数据一旦产生上溢，计算机必须中断运算操作，进行溢出处理，当运算结果在 0 至最小正数之间时称为正下溢，在 0 至绝对值最小负数之间时称为负下溢，正下溢和负下溢统称为下溢。数据下溢时，浮点数值趋于零，计算机仅将其当作机器零处理。
IEEE 754 标准
| 类型 | 数符 | 阶码 | 尾数数值 | 总位数 | 偏置值 | |
| 十六进制 | 十进制 | |||||
| 短浮点数（FLOAT） | 1 | 8 | 23 | 32 | 7FH | 127 |
| 长浮点数（DOUBLE） | 1 | 11 | 52 | 64 | 3FFH | 1023 |
| 临时浮点数 | 1 | 15 | 64 | 80 | 3FFFH | 16383 |
| 数符 | 阶码 | 尾数 |
计算所得阶码需加上偏置值，以移码形式表示。对于规格化的二进制浮点数，数值的最高位总是“1”，为了能使尾数多表示一位有效位，将这个“1”隐含，因此尾数数值实际上是24位。
阶码以移码形式表示，尾数以原码形式表示。
阶码全 1 表示无穷大，全 0 表示非规格化数。
浮点数的加减运算：（1）对阶。小阶向大阶看齐。（2）尾数求和（3）规格化（4）舍入。“0”舍“1”入法；恒置“1”法。（5）溢出判断（6）强制类型转换
采用规格化的浮点数主要是为了增加数据的表示精度。
对阶操作不存在阶码减小（小阶向大阶看齐）。
舍入是浮点数的概念，定点数没有舍入的概念。浮点数舍入的情况有两种：对阶、右规格化。
对阶操作不会引起阶码上溢或下溢。右规和尾数舍入都可能引起阶码上溢。左规时可能引起阶码下溢。尾数溢出时结果不一定溢出。
设阶码和尾数均用补码表示，阶码部分共 K + 1 位（含 1 位阶符），尾数部分共 n + 1 位（含 1 位数符），则
| 浮点数 | 浮点表示 | 真值 | |
| 阶码 | 尾数 | ||
| 最大正数 | 01...1 | 0.11...11 | (1 - 2-n) * 2^(2k - 1) |
| 绝对值最大负数 | 01...1 | 1.00...00 | -1 * 2^(2k - 1) |
| 最小正数 | 10...0 | 0.00...01 | 2-n * 2^(-2k) |
| 规格化的最小正数 | 10...0 | 0.10...00 | 2-1 * 2^(-2k) |
| 绝对值最小负数 | 10...0 | 1.11...11 | -2-n * 2^(-2k) |
| 规格化的绝对值最小负数 | 10...0 | 1.01...11 | -(2-1 + 2-n) * 2 ^(-2k) |
算术逻辑单元（ALU）
1. 一位全加器
全加器（FA）是最基本的加法单元，有加数 Ai、加数 Bi 与低位传来的进位 Ci-1 共三个输入有 本位和 Si 与向高位的进位 Ci 共两个输出。
和表达式：Si = Ai ⊕ Bi ⊕ Ci-1 (Ai、Bi、Ci-1 中有奇数个 1 时，Si = 1；否则 Si = 0)
进位表达式：Ci = AiBi + (Ai ⊕ Bi)Ci-1
2.串行加法器
在串行加法器中，只有一个全加器，数据逐位串行送入加法器中进行运算。若操作数长 n 位，则加法器就要分 n 次进行，每次产生一位和，并且串行逐位送回寄存器。进位触发器用来寄存进位信号，以便参与下一次运算。
串行加法器具有器件少、成本低的优点，但运算速度慢，多用于某些低速的专用运算器。
3.并行加法器
并行加法器由多个全加器组成，其位数与机器的字长相同，各位数据同时运算。并行加法器中的每个全加器都有一个从低位送来的进位输出和一个传送给高位的进位输出，通常将传递进位信号的逻辑线路连接起来构成的几位内网络称为进位链。
并行加法器的进位通常分为串行进位与并行进位。
- 串行进位。把 n 个全加器串接起来，就可以进行两个 n 位数的相加，这种加法器称为串行进位的并行加法器。串行进位又称行波进位，每级进位直接依赖于前一级的进位，即进位信号是逐级形成的。如图：
- 并行进位。并行进位又称先行进位、同时进位，其特点是各级进位信号同时形成。
- 上述各式所有的进位输出仅由 Gi、Pi及最低进位输入 C0 决定，而不依赖于其低位的进位输入 Ci-1 ，因此各级进位输出可以同时产生。这种进位方式是快速的，与字长无关。
分组并行进位方式，把 n 位全加器分为若干小组，小组内的各位之间实行并行快速进位，小组与小组之间可以采用串行进位方式，也可以采用并行快速进位方式，因此有以下两种情况：
ALU 是一种功能较强的组合逻辑电路。
74181 为 4 位并行加法器，其 4 位进位是同时产生的，用 4 片 74181 芯片可组成 16 位 ALU。其片内进位是快速的，但片间进位是逐片传递的，即组内并行（74181 片内）、组间串行（74181 片间）。
若把 16 位 ALU 中的每 4 位作为一组，即将 74181 与 74182 芯片（先行进位芯片）配合，用类似位间快速进位的方法来实现 16 位 ALU（4 片 ALU 组成），则能得到 16 位的两级先行进位 ALU，即组内并行（74181 片内）、组间并行（74181 片间）。
在串行进位的并行加法器中，影响加法器运算速度的关键因素是进位传递延迟。
地址寄存器不属于运算器，而属于存储器。状态寄存器、数据总线、ALU 均是组成运算器的部件。