Computer Composition Principles Study Notes - Adder

Arithmetic Logic Unit ALU

In addition to some necessary registers inside the arithmetic unit, the core component used to implement operations is the arithmetic logic unit (ALU).
ALU mainly has the following functions:

• Arithmetic operations: addition, subtraction, multiplication, division, etc.
• Logical operations: AND, OR, NOT, EXCLUSIVE OR, etc.
• Auxiliary functions: shift, complement, etc.

The general structure of the ALU is as follows:

$A_i$和$B_i$For the input signal, for example, to realize the addition of two 8-bit binary numbers, then one of them is from $A_i$input from $B_i$Terminal input, the essence of the input is some electrical signal (high and low level), the output signal (operation result) from $F_i$terminal output, $K_i$It is a control signal issued by the control unit CU.

Example: 74181 chip S

on the right side $S_3{S}_2{S}_{1}M$ is the control signal from the control unit, the control unit will be responsible for analyzing the meaning of the command, and then send some control signals according to the meaning of the command, such as: M = 1 , S 3 S 2 S 1$M=1,S_3{S}_2{S}_1{S}_0=When\; 1001$ , do logical operation$A\oplus B$,$S_3{S}_2{S}_1{S}_0$There are 4 bits of information, that is, corresponding to $2^4=16$ states, indicating that the chip supports 16 arithmetic operations or 16 logic operations. $A_i、B_{i}and{F}_i$Corresponding to the previous figure are the input signal and output signal respectively.

The word length of the machine refers to how many bits of integer operations the computer can handle at the same time, that is, how many bits of information can be input at the same time in the ALU. Generally speaking, how many bits of data the ALU can handle, usually the register $The\; number\; of\; bits\; of\; X$ is consistent with the number of bits of ALU. In the picture above, the ALU inputs two 4-bit information, and then outputs a 4-bit operation result. This result must be put back into a certain register. In order to allow the ALU to perfectly match the register, how many bits are the ALU, and the register It also corresponds to how many bits are designed.

The output signal on the left and $C_{-1}$The input signal is designed for series connection with other chips.

The most basic logical operations

A and B are input signals and Y is an output signal. For example, for an AND gate, if A inputs a 5V electrical signal as 1, and B inputs a 1V electrical signal as 0, then Y will output a 1V electrical signal as 0, that is, 1 and 0 phase and get 0. Note: NOT
gate There is a small circle on the right side of the circuit diagram.

Analog multiplication, addition

• Priority of AND operation and OR operation: AND > OR (Eg: AB+CD calculates AND first, then OR)
• A(C+D)=AC+AD ——distributive law
• ABC=A(BC) - associative law
• A+B+C=A+(B+C) ——associative law

What's the point?
In essence, logical expressions are mathematical descriptions of circuits. Simplifying logical expressions is simplifying circuits, and these devices need money, so simplifying circuits is saving money.
Example:
The circuit realizes AC+AD=A(C+D).
It can be seen that the implementation on the right has one less AND gate than the implementation on the left.

compound logic operation

Inversion rate (DeMorgan rate): $\overline{A+B}=\overline{A}\cdot \overline{B},\overline{A\cdot B}=\overline{A}+\overline{B}$

Any use of AND, OR, NOT to implement XOR operations?
->A and B are different, then it is 1
->A=0 and B=1 or A=1 and B=0
-> $\overline{A}\cdot B+A\cdot \overline{B}$
Circuit implementation:

Using a gate circuit to find an even parity bit

The natural logic of "exclusive or": "addition" and "parity check" even
check means that when we add this check bit, overall, the number of 1s has an even number.

The logic of the even parity corresponds to the logic of the XOR, and the XOR is performed on an even number of 1s, and the final result is 0, which corresponds to the parity bit that the even parity needs to obtain. The logic of the odd parity corresponds to the logic of the XOR, and the XOR is performed on an odd number of 1s, and the final result is 0, which corresponds to the parity bit that the odd parity needs to obtain.

The circuit diagram of the following parity bit:

one bit full adder

How does the XOR gate implement the addition operation?
Start with adding by hand.

$S_{i}and{C}_i$How to determine?
When there is an odd number of 1s in the input, $S_i$is 1 (different) $S_i=A_i\oplus B_i\oplus C_{i-1}$; There are two cases $C_i$is 1, the first type is that the two standards are 1, that is, $A_i{B}_i$都的1，即$A_i{B}_i=1$ , another case is that one of the two standard bits is 1, and the carry from the lower bit$C_{i-1}$is 1, immediately $(A_i\oplus B_i)C_{i-1}=1$ .

According to these two logical expressions, the corresponding circuit can be obtained, as shown in the figure below.

This is a one-bit full adder. According to the two basic bits and the low-order carry as input, the basic bit and$S_i$and the carry to high bit $C_i$, simplify the above figure and shield its internal circuit details, as shown in the figure below

serial adder

Next, let's look at how to use a full adder to implement multi-bit addition.
As the name suggests, the so-called serial is to add bit by bit, adding a carry trigger to save the carry bit, so as to realize adding bit by bit.

$A_i{B}_i{C}_{i-1}$S i S_i can be determined by a full adder$S_i$and $C_i$，$C_i$Save it to the carry flip-flop, and then you can input higher-order information $A_{i+1}{B}_{i+1}{C}_i$,$C_i$The value of comes from the carry flip-flop as the input signal, and so on.

Serial adder: There is only one full adder, and the data is serially sent to the adder bit by bit for operation. The carry flip-flop is used to register the carry signal so as to participate in the next operation.
If the operand is n bits long, the addition will be divided into n times, each time a one-bit sum is generated, and it is serially sent back to the register bit by bit, so the efficiency of this serial adder is relatively low.

parallel adder

Parallel adder with serial carry: By connecting n full adders in series, two n-digit numbers can be added.

In this way, two n-bit numbers can be input at the same time. The two operands A and B have n bits. The corresponding bits of each group will be added by the full adder, and the carry generated by the addition of the low bits will be used as For the input signal of the next full adder, although we can input the information of each value of the two numbers A and B at the same time at the beginning, the actual operation speed of the electrical appliance is very fast, however, the transmission of these electrical signals still takes time , that is to say, only after the execution of the lower-order operation is completed, can it be determined what signal should be carried to the high-order. If the signal to the high-order is changed, the high-order sum and the higher-order carry signal will changes happened. Therefore, this kind of parallel adder is called a serial carry parallel adder, and the carry information is serially forwarded bit by bit.

Serial carry and wave carry, each carry directly depends on the carry of the previous stage, that is, the carry signal is formed bit by bit, so the operation speed of this adder depends largely on the generation speed of each carry and transfer speed. How to optimize this problem?

ALU improvements

How to generate carry faster? Let's divide the carry $C_i$The expression expansion of :

If $C_i$Expand all the time, one day you can expand to $C_0$, while $C_0$It's the information you have from the very beginning.

Conclusion: Carry $C_i$It can be combined with C 0 C_0 according to the 1st~i bits of the summand and the addend$C_0$to be sure.

记$G_i=A_i{B}_i,P_i=A_i\oplus B_i$, get the following expression:


From the above expansion, we can see that even if we want to calculate $C_4$For this carry information, all the data required for the calculation are prepared at the beginning, then only need to design the corresponding circuit according to the expression to directly calculate the value of the full adder at the fourth full adder. In this design, almost every bit of carry information is generated at the same time, and there is no need to wait for the following carry bits to be uploaded one by one like the previous design, so the calculation speed of this adder will be much faster. We call it a parallel adder with parallel carry: the carry signals of all levels are generated at the same time, and there are called advanced carry and simultaneous carry.

Flaws of this design: From $C_{1}to{C}_4$We once nested dolls, the deeper the nest, the longer the logical expression and the more complicated the circuit.

The more classic way you do it is to set to $C_4$position, that is, it can support 4-bit plus 4-bit operations.

If we need more bits for addition, we only need to connect the 4-bit CLA adders in series.

Optimization of Parallel Adder

The single-stage look-ahead carry mode is also called intra-group parallel and inter-group serial carry mode.

Carry within a group can be obtained at the same time, but the carry between groups will cause the previous problem, that is, the $C_4$, the second set of $C_8{S}_8{S}_7{S}_6{S}_5$Only then can it be determined that it needs to be forwarded step by step, so how to optimize this problem?
Continue nesting dolls! ! !

记$G_1^{\ast }=G_4+P_4{G}_3+P_4{P}_3{G}_2+P_4{P}_3{P}_2{G}_1；$
$P_1^{\ast }=P_4{P}_3{P}_2{P}_1$


Core feature: G i ∗ P i ∗ G_{i}^{*}P_{i}^{*} of this group can be determined according to the 4×2 input bits of this group$G_i^{\ast }{P}_i^{\ast }$.

The operation rules of the inter-group carry information and the operation rules of the intra-group carry information can be completely corresponded $G_1^{\ast }、P_1^{\ast }、G_2^{\ast }、P_2^{\ast }、G_3^{\ast }、P_3^{\ast }、G_4^{\ast }、P_4^{\ast }$As the input of CLA, the circuit inside CLA can help us complete the $C_4、C_8、C_{12}、C_{16}$operation.

Optimization of ALU chip

Modify the above circuit, group each 4 bits into a group, perform 4bit+4bit operation, modify the internal circuit of CLA (BCLA), let it output G i ∗ and P i ∗ G_{i of this $G_i^{\ast }and{P}_i^{\ast }$, after $G_i^{\ast }and{P}_i^{\ast }$As the input of the CLA circuit, and inside the CLA , C 4 , C 8 , C 12 , C 16 C_4, C_8, C_{12}, C_{16} can be obtained in parallel$C_4、C_8、C_{12}、C_{16}$The value of each group, that is, the carry information that needs to be used as a reference when calculating the basic sum of each group does not need to wait to be transmitted from the back one by one as before, so using this idea to realize the circuit can realize intra-group parallelism, In the parallel carry mode, the carry information required by each group is generated in parallel, so the operational efficiency of the circuit is improved again.

The 74181 chip supports 4-bit addition operations, $C_{n+4}$Carry to a higher bit after adding two 4-bit bit information, $C_{-1}$is the carry from the lower bit.

Therefore, using the line to serialize four 74181s can realize a 16-bit intra-group parallel and inter-group serial carry ALU.

If another SN74182 chip is connected, then we can realize a 16-bit carry ALU that is parallel within a group and parallel between groups.

Summary: Serial adder→parallel adder with serial carry→adder with intra-group parallel and inter-group serial carry→adder with intra-group parallel and inter-group parallel carry

learning reference

Wangdao postgraduate entrance examination: https://www.bilibili.com/video/BV1BE411D7ii?p=27&vd_source=795c0ddf50db35d4812a24c0bc3c09f4