5-2 Central Processing Unit - Data Flow of Instruction Cycle

1. Instruction cycle

Instruction cycle: The total time required for the CPU to fetch and execute an instruction from main memory.

Here: instruction fetch cycle = instruction fetch + instruction decoding

The instruction cycle is often represented by several machine cycles/CPU cycles. A machine cycle includes several clock cycles/beats/T cycles/CPU clock cycles. The clock cycle is the most basic unit of CPU operation.

Review: CPU execution time = number of clock cycles × clock cycle = CPI × number of instructions × clock cycle

It can be seen that the number of machine cycles in each instruction cycle can be different, and the number of beats in each machine cycle can also be different. Let's take an example

1. The empty instruction NOP
fetches the instruction and does not operate. That is, instruction cycle = fetch cycle (including fetch cycle and analysis instruction). Contains 1 machine cycle

2. The addition instruction ADD
instruction cycle = instruction fetch cycle + execution cycle
contains 2 machine cycles, and the number of beats contained in the two machine cycles may be different
(if it is a multiplication instruction, the execution cycle is longer)

3. Instructions with indirect addressing Instruction
cycle = instruction fetch cycle + inter-address cycle + execution cycle
Contains 3 machine cycles, and the number of beats contained in the three machine cycles may be different

(Figure: an indirect addressing)

4. Instructions with an interrupt cycle
Instruction cycle = instruction fetch cycle + inter-address cycle + execution cycle + interrupt cycle
At the end of each instruction, it is necessary to check that the interrupt
contains 4 machine cycles, four machine cycles The number of beats included may vary

Summarize

The trigger can be used to determine which cycle is currently in

2. Data flow

1. Instruction fetch cycle

The content in the PC is taken out of the instruction code from the main memory and stored in the IR, which may be accessed due to instruction fetching.

Data flow direction:
①The content pointed to by PC is transmitted to MAR through the address bus, that is, (PC)→MAR
②CU sends a control signal to the main memory through the control bus (such as: read signal)
③The main memory searches the memory bank according to the address information recorded by MAR Output the binary data corresponding to the address, and put the data into MDR through the data bus, that is, M(MAR)→MDR
④The instructions in MDR are put into IR through the internal bus (where MDR belongs to the CPU), that is, (MDR)→IR
⑤ Every time an instruction is fetched, the CU sends a control signal to form the address of the next instruction and let the PC point to it, that is, (PC)+"1"→PC

Or
PC → MAR → address bus → main memory
CU sends control signal → control bus → main memory
main memory → data bus → MDR → IR
CU sends read command → PC content plus 1

2. Indirect cycle

The task of the indirect cycle is to fetch the effective address of the operand, which may be accessed because of the effective address.

Data flow direction:
① Send the address code Ad in the instruction to MAR and send it to the address bus, that is, Ad(IR)→MAR→address bus
Note: The IR here can be changed to MDR, and the two currently store the same content
②CU passes The control bus sends a control signal (such as a read command) to the main memory, that is, the CU sends a control signal → control bus → main memory
③ The main memory finds the binary data corresponding to the address in the memory bank according to the address information recorded by MAR, and passes through the data bus Put the data in MDR, that is, M(MAR)→MDR
④ Send the effective address to the address code field of the instruction, that is, (MDR)→Ad(IR)

3. Execution cycle

The task of the execution cycle is to generate an execution result through the ALU operation according to the operation code and the operand of the instruction word in the IR. May be accessed due to operand fetches

The execution cycle operations of different instructions are different, and there is no unified data flow direction

4. Interrupt cycle

Suspend the current task to complete other tasks, which may be accessed due to power failure of the save program

In order to be able to resume the current task, the breakpoint needs to be saved. Generally, the stack is used to save the breakpoint. Here, SP is used to point to the address of the storage unit at the top of the stack. The address space of the stack is arranged from high to low. Assuming that SP points to the top element of the stack, when pushing into the stack, SP-1, and then store data.

Data flow direction:
PC automatically adds "1" to point to the next instruction to be executed, and an interrupt is sent at this time. In order to save the breakpoint, the value of the PC needs to be pushed into the main memory, and then turned to point to the interrupt handler
①CU controls SP-1, inserts the PC at the address pointed to by the current SP, and needs to send the address pointed to by the SP to MAR and to the address bus , that is (SP)-1→SP, (SP)→MAR
②CU sends a control signal (write command) to the main memory through the control bus, that is, the CU sends a write command→control bus→main memory
③Write PC into the main memory, that is (PC)→MDR→data bus→main memory
④CU changes PC to the address of the first instruction of the interrupt handler, that is, CU→PC

3. Instruction execution plan

An instruction cycle usually includes several time periods (execution steps), each step completes a part of the function of the instruction, and several steps executed in sequence complete the entire function of the instruction.

There are 3 options to arrange the execution steps of the instruction:

1. Single instruction cycle

All commands use the same execution time. Instructions are executed serially, that is, the next instruction can only be started after the execution of the previous instruction is completed. In order to ensure that each instruction is completed within a fixed clock cycle, it is necessary to select the execution time of the longest instruction when designing the execution time, which will cause instructions that could have been completed in a shorter time to use a longer cycle to complete , reducing the speed of the entire system.

2. Multiple instruction cycles

Different execution steps are selected for different types of instructions. Instructions are executed serially, but it is no longer required that all instructions occupy the same execution time, that is, on-demand allocation. However, more complex hardware design is required and the cost is higher.

3. Pipeline solution

A scheme in which instructions can be executed in parallel. This scheme allows multiple instructions to run at the same time as much as possible by starting an instruction every clock cycle, but each is in a different execution step. The goal it pursues is to strive to complete the execution process of an instruction in each clock pulse cycle.

• Explain the clock cycle, instruction cycle, machine cycle and the relationship between them
  ①The total time required by the CPU to fetch and execute an instruction is called the instruction cycle, and the instruction cycle is often composed of several machine cycles; ②The machine cycle is a synchronously controlled machine Among them, the time required to execute a relatively complete operation in the instruction cycle, such as fetching instructions, fetching effective addresses, and executing instructions. Usually machine cycle length = main memory cycle. A machine cycle includes several clock cycles; ③ clock cycle refers to the cycle time of the computer's main clock, which is the most basic unit of CPU operation, corresponding to the time required to complete a micro-operation, usually clock cycle = the reciprocal of the computer's main frequency.
• How many machine cycles does a computer instruction have?
  An instruction contains up to 4 machine cycles. For example, there is 1 empty instruction, 2 addition instructions, 3 instructions with indirect addressing, and 4 instructions with medium and short cycles.
• What is an instruction cycle? Is there a fixed value for the instruction cycle? Why?
  An instruction cycle is the time required to fetch and execute an instruction. Since the time required to execute various instructions in the computer varies greatly, in order to improve the CPU operating efficiency, even in synchronously controlled machines, the instruction cycle lengths of different instructions are inconsistent, that is to say, the instruction cycle is different for different instructions. is not a fixed value.