Verilog study notes (2): Verilog programming statements and description methods

Chapter 2 Verilog programming statement and description method

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1. Data flow modeling

1.1 Continuous assignment statement

• The target types of continuous assignment are mainly scalar line network and vector line network.
  (1) Scalar wire network, such as: wire a,b;
  (2) Vector wire network, such as: wire [3:0]a,b;
• Explicit continuous assignment statement:
  <net_declaratlon><range><name>;
assign #<delay><name> = Assignment expression;

module exa1(a,b,m,n,c,y,w); 
	input[3:0]a,b,m,n; 
	output[3:0]c,y; 
	wire[3:0]a,b,m,n,c,y;
	assign y = m|n;
	assign #(3,2,4) c = a&b;
endmodule

• Implicit continuous assignment statement:
  <net_declaration><drive_strength><range>#<delay><name> = Assignment expression;

module exa2(a,b,m,n,c,y,w); 
	input[3:0]a,b,m,n; 
	output[3:0]c,y,w; 
	wire[3:0]a,b,m,n; 
	wire[3:0] y = m|n;
	wire[3:0]#(3,2,4) c=a&b;
	wire(strong0,weakl) [3:0] #(2,l,3) w = (a^b)&(m^n);  
endmodule

<net_declaratlon> : Wire type variable type
<range> : variable bit width, which specifies the width of the variable data type, the format is [msb:lab], the default is 1.
<drive_strength> : Assignment drive strength, optional, can only be specified in the "implicit continuous assignment statement" format. It is used to specify the driving strength to which a wired variable is subjected. For example: wire (weak0, strong1) out = in1&in2;
<delay> : delay amount, optional. #(delay1, delay2, delay3,...).

• The following points need to be paid attention to in the continuous assignment statement :
  1. The assignment target can only be the wire network type (wire).
  2. In continuous assignment, as long as any variable of the expression on the right side of the assignment statement changes, the expression will be calculated immediately, and the result of the calculation will be assigned to the signal on the left immediately (if no delay is defined).
  3. Continuous assignment statements cannot appear in process blocks.
  4. There are parallel statements between multiple continuous assignment statements, so it has nothing to do with the position order.
  5. The delay in the continuous assignment statement has the characteristics of the inertial delay in the hardware circuit. Any signal change pulses shorter than the delay will be filtered out and will not be reflected on the output port.

2. Behavior-level modeling

category	statement	Synthesizable
procedural statement	initial
	always	√
statement block	Serial block begin-end
	Parallel block fork-join
assignment statement	Continuous assignment assign	√
	Process assignment =,<=	√
Conditional statements	if-else	√
	case，casez，casex	√
loop statement	forever
	repeat
	while
	for	√
loop statement	`define	√
	`include	√
	`ifdef,`else,`endif	√

2.1 Procedural statements

• 1.initia process statement
  
  
• 2. The always statement block
  From the perspective of grammatical description, compared with the initial process block, the trigger state of the always statement block always exists. As long as the sensitive event list behind the always is satisfied, the process block will be executed.
  Its grammatical format is:
  always@(<敏感事件列表>) 语句块;
  For example:

@(a)  //当信号a的值发生改变时
@(a or b) //当信号a或信号b的值发生改变时
@(posedge clock) //当clock的上升沿到来时
@(negedge clock) //当clock的下降沿到来时
@(posedge clk or negedge reset) //当clk的上升沿到来或reset信号的下降沿到来时

• 3. Problems needing attention in the use of procedural statements
     In terms of signal definition form, Verilog HDL requires that in procedural statements (initial and always), assigned signals must be defined as "reg" types, whether for sequential logic or combinational logic description.
     In terms of the sensitive event table, this is a key land design in the Verilog HDL language. How to select sensitive events as the triggering conditions of the process has certain design requirements in the Verilog HDL program.
     (1) When using a process to describe a combinational circuit, all input signals need to be included in the list of sensitive signals.
     (2) When using the process to describe the sequential circuit, it is necessary to include the time signal and some input signals in the list of sensitive signals. It should be noted that different sensitive event lists will result in different circuit forms.

For example: use the initial statement to generate a test signal

For example: use the always statement to describe the 4-to-1 data line selector.

For example: use the always statement to describe synchronous setting and synchronously clear the counter

For example: use the always procedure statement to describe the asynchronous clearing of the counter

2.2 Statement block

• Statement blocks include serial statement blocks (begin-end) and parallel statement blocks (fork-join).

  • The serial statement block uses the keywords 'begin' and 'end', and the statements in it are executed sequentially in a serial manner, which can be used in synthesizable circuit programs and simulation test programs. Its syntax format is:
    

    • The serial statement block has the following characteristics:
      (1) Each statement in the serial statement block is executed one by one according to the sequence in the block. The delay given by each statement in the block is relative to the execution completion time of the previous statement.
      (2) The start execution time of the serial statement block is the time when the first statement in the serial statement block starts to execute. The end time of a serial statement block is the time when the execution of the last statement in the block ends.

  • Parallel statement blocks use the keywords "fork" and "join", and the statements in them are executed concurrently in a parallel manner. They can only be used in simulation test programs, not in synthesizable circuit programs. Its grammatical format is:
    

    • Parallel statement blocks have the following characteristics:
      (1) The statements in the block are executed simultaneously, that is, as soon as the program flow control enters the parallel statement block, the statements in the block start to be executed in parallel at the same time.
      (2) The delay time of each statement in the block is relative to the simulation time when the program flow control enters the block.

Take the following example:

the waveform simulation diagram is as follows:

Comparison of the two methods:

2.3 Procedure assignment statement

• There are two forms of procedure assignment statement: blocking procedure assignment statement and non-blocking procedure assignment statement.
  • The operation symbol of the blocking assignment statement is "=", and the syntax format is:
    变量 = 表达式；
    for example: b= a;
    • The blocking assignment statement has the following characteristics:
      (1) In the serial statement block, each blocking assignment statement will be executed in sequence; in the parallel statement block, each blocking assignment statement will be executed at the same time, without sequence;
      ( 2) The order of executing the blocking assignment statement is to first calculate the value of the expression on the right side of the equal sign, and then immediately assign the calculated value to the variable on the left, which has nothing to do with the simulation time.
  • The operation symbol of the non-blocking assignment statement is "<=" The syntax format is:
    变量 <= 表达式;
    for example: b<= a,
    • The non-blocking assignment statement has the following characteristics:
      (1) In the serial statement block, the execution of each non-blocking assignment statement has no order, and the statement in the front will not affect the execution of the following statement. Parallel execution;
      (2) The order of executing non-blocking assignment statements is to first calculate the value of the expression on the right, and then assign the calculated value to the variable on the left when the delay time is over.

The following example explains in detail:

In the above two programs, the basic description is the same, the difference is that program (1) uses a blocking assignment statement, while program (2) uses a non-blocking assignment statement.

If a blocking assignment statement is used to describe the circuit of program (2), its Verilog program code is:

Another example is as follows:

2.4 Procedural continuous assignment statement

• In Verilog, there are two types of procedural continuous assignment statements: assignment and reassignment statements (assign, deassign) and force and release statements (force, release).
• The keywords used in the assignment statement and the reassignment statement are "assign" and "deasslgn" respectively. The grammatical formats are as
  assign <寄存器型变量> = <赋值表达式>；
deassign <寄存器型变量>；
  follows:
  
• The keywords "force" and "release" adopted by the force statement and the release statement can perform assignment operations on connection type and register variable type, and the priority of the "force" statement is higher than that of the "assign" statement. The syntax formats are:
  force <寄存器或连线型变量> = <赋值表达式>;
release<寄存器或连线型变量>；

2.5 Conditional branch statement

• There are two kinds of conditional branch statements in Verilog HDL: if conditional statement and case conditional branch statement.

  • 1. If conditional statement
    The if conditional statement is to judge whether the given condition is satisfied, and then determine the next step according to the result of the judgment.
    
    For example:
    
    

    • Nesting of one or more if statements is allowed in the if statement, and the syntax format is:
      
  • 2. Case conditional branch statement
       Compared with the if statement with only two branches, the case statement is a statement that can realize multi-way branch selection control, which is more convenient and intuitive than the if-else conditional statement. Generally, the case statement is mostly used in the design of multi-conditional decoding circuits. The grammatical format of the case statement is:
       
       the following is the truth table of case, casez, and caseex, which is used to judge whether the expression and value are satisfied:

case	0	1	x	z
0	1	0	0	0
1	0	1	0	0
x	0	0	1	0
z	0	0	0	1

cram	0	1	x	z
0	1	0	0	1
1	0	1	0	1
x	0	0	1	1
z	1	1	1	1

casex	0	1	x	z
0	1	0	1	1
1	0	1	1	1
x	1	1	1	1
z	1	1	1	1

• Pay attention to the use of case statements:
  (1) The value 1 to value n must be different. Once the value is determined to be the same as a certain value and the corresponding statement block is executed, the execution of the case statement will end.
  (2) If several consecutive value items execute the same statement, these value items can be separated by commas, and the statement is placed in the last of these value items.
  (3) The default option is equivalent to the else part in the if-else statement, which can be used or not used according to the needs. When all possible values ​​​​of the sensitive expression have been listed, the default can be omitted.
  (4) The bit widths of the values ​​of all the expressions in the case statement must be equal, only in this way can the control expression and the branch expression compare the corresponding bits.
  For example: use the case statement to describe the BCD digital decoding tube

When using the case statement, all states should be included. If not included, the default item must be written, otherwise a latch will be generated, which is not allowed in synchronous sequential circuit design.

2.6 Loop Statements

• 1. Forever loop statement
  The loop statement guided by the keyword "forever" means a forever loop. Do not include any conditional expressions in the forever loop, just execute an infinite loop until a system task is encountered $finish. If you need to exit from the forever loop, you can use the disable statement. The grammatical format of the forever statement is:
  forever 语句或语句块;
  Example: use the forever statement to generate a clock signal
  
• 2. Repeat loop statement
  The loop statement guided by the repeat loop statement keyword "repeat" means to execute a fixed number of loops. Its grammatical format is:
  repeat (循环次数表达式) 语句或语句块;
  For example, use the repeat cycle to generate a fixed-period clock signal
  
• 3. while loop statement The
  loop statement guided by the keyword "while" represents a "conditional loop". The while statement determines the execution of the loop body according to the true or false of the conditional expression. When the specified conditional expression takes a value of Only when it is true will the loop body be executed repeatedly, otherwise the loop body will not be executed. The syntax format is:
  while(条件表达式) 语句或语句块;
  For example, use the while statement to generate a clock signal
  
• 4. For loop statement
  The loop statement to be guided by the loop statement keyword "for" also represents a "conditional loop", which is only looped when the specified conditional expression is true, and its grammatical format is:for(循环变量赋初值; 循环结束条件; 循环变量增值) 语句块;
  

3. Structured Modeling

The structure description method is to describe the hardware circuit as a hierarchical sub-module system, and call these modules layer by layer to form a description method of digital logic circuits and systems with complex functions. In this description method, the mutual hierarchical relationship and interconnection relationship between the various sub-modules that make up the hardware circuit need to be explained.
According to the different abstraction levels of the called sub-modules, the structure description methods of the modules can be divided into the following three categories:
<1) Module-level modeling: describe the hardware circuit structure by calling the low-level sub-modules generated by the user design. A case module consists of instances of lower-level modules.
(2) Gate-level modeling: The structure of the hardware circuit is described by calling the basic gate-level components inside Verilog. In this case, the module will be composed of instances of the basic gate-level components.
(3) Switch-level modeling: The structure of the hardware circuit is described by calling the basic switch elements inside Verilog. In this case, the module will be composed of instances of the basic switch-level elements.

3.1 Module-level modeling

Module-level modeling is to describe the hardware circuit structure and design the circuit by calling the module module generated by the user's own description.
The module modeling method can regard a module as being built up like building blocks by other modules. The called module in the module belongs to the lower-level module. If the current module is no longer called by other modules, then this module must be the so-called top-level module. In the description of a hardware system, there must be one and only one top-level module.

• 1. Module calling method
  In Verilog HDL, a module can be called by any other module. This call actually copies and connects the circuit described by the module. The basic grammatical format of module calling is: 模块名 <参数值列表>实例名(端口名列表);
  For example:
  
  if the same module is called several times in the current module, it needs to be identified with different instance names, but it can be defined in the same module calling statement, as long as the respective instances Name and port name lists are separated by commas. The basic syntax format is:
  <参数值列表>实例名1 (端口名列表1),
<参数值列表>实例名2 (端口名列表2),
... ...
<参数值列表>实例名n (端口名列表n);
  in the above format, the module name is the called module, the parameter value list is optional, the instance name represents the generated module instance, and the instance names must be different, and the port list indicates the module instance and external signal Connection.
  For example, in the above example, if you want to call more 2-input AND gates to achieve more complex functions, you can use the following multiple module instance statements: When you need to call the same module multiple times, you can also
  
  use Call the module in the way of array call, and the syntax format of the array call is as follows:
  <被调用模块名><实例阵列名>[阵列左边界:阵列右边界](<端口连接表>);
  "Array left boundary" and "Array right boundary" are two constant expressions, which are used to specify the size of the module instance array generated after the call.
  For example, use the module instance statement of the array call method to describe the structure:
  
  
• 2. Module port correspondence mode
  (1) Port position correspondence mode
  The port position correspondence mode is a module calling mode in which the called modules appear in the port connection table in a certain order. Its grammatical format is:
  模块名<参数值列表>实例名(<信号名1>，<信号名2>，...，<信号名n>);
  For example, use a 1-bit half-adder to form a 1-bit full-adder using a modular structure modeling method

//半加器模块
module halfadder(a,b,s,c);
input a,b;
output c,s;
	assign s = a^b;
	assign c = a&b;
endmodule

//全加器模块
module fulladder(p,q,ci,co,sum);
input q,p,ci;
output co,sum;
wire w1,w2,w3;
	halfadder U1(p,q,w1,w2);
	halfadder U2(ci,w1,sum,w3);
	or U3(co,w2,w3);
endmodule

(2) Corresponding method of port name The
corresponding method of port name is another module calling method allowed by Verilog, and its grammatical format is as follows:
模块名<参数值列表> 实例名(.端口名1<信号名1> , .端口名2<信号名2>, ... , .端口名n<信号名n>);
For example: an example of calling a module corresponding to a port name

module dff(d,clk,clr,q);//D触发器模块，时被调用的模块，属于底层模块
input d,clk,clr;
output q;
reg q;
always@(posedge clk or negrdge clr)
	begin
		if(!clr)
			q = 0;
		else
			q = d;
	end
endmodule

module shifter_D(din,clock,clear,out);//顶层模块，用来调用底层模块
inprt din,clock,clear;
output [3:0] out;
	dff U1(.q(out[0]),.d(din),.clk(clock),.clr(clear));
	dff U1(.q(out[1]),.d((out[0]),.clk(clock),.clr(clear));
	dff U1(.q(out[2]),.d((out[1]),.clk(clock),.clr(clear));
	dff U1(.q(out[3]),.d((out[2]),.clk(clock),.clr(clear));
endmodule

(3) Matching of different port widths
There is an implicit continuous assignment statement between ports and port expressions. Therefore, when the bit width of the port and the port expression are inconsistent, the port will be matched, and the bit width matching rule adopted is the same as that used for continuous assignment.
For example: the matching problem of different bit widths when the module is called

• 3. Module parameter value
  The parameter value of the module instance can be changed in the following two ways, respectively using the module instance statement with parameters to modify the parameter value and using the definition parameter statement (defparam statement) to modify the parameter value.
  (1) Use the module instance statement with parameters to modify the parameter value. In this method, the module instance itself can specify a new parameter value. The syntax format is: The parameter value list is divided into position correspondence and name
  模块名<参数值列表> 调用名(端口名列表);
  correspondence two ways.
  For example: module call to change parameter value
  
  (2) Use definition parameter statement (defparam statement) to modify parameter value
  The second method to change the parameter value in the called module when making module call is to use "parameter redefinition statement" (defparam statement). The grammatical format of the parameter redefinition statement is:
  
  It should be noted that the parameter name must be in the form of a hierarchical path in order to lock which module the parameter to be modified belongs to.
  Example: Use the defparam statement to modify parameter values

module halfadder(a,b,s,c);//半加器模块
input a,b;
output c,s;
parameter xor_delay = 2, and_delay = 3;
	assign #xor_delay s=a^b;
	assign #and_delay c=a&b;
endmodule

module fulladder(p,q,ci,co,sum);//全加器模块
input p,q,ci;
output co,sum;
parameter or_delay = 1;
wire w1,w2,w3;
	halfadder U1(p,q,w1,w2);
	halfadder U2(ci,w1,sum.w3);
	or #or_delay U3(co,w2,w3);
endmodule

module top1(top1a,top1b,top1s,top1c);//修改半加器模块参数的模块top1
input top1a,top1b;
output top1s,top1c;
	defparam U1.xor_delay = 4, U1.and_delay = 5;//名为U1的半加器实例中对参数xor_delay和参数and_delay值的修改
	halfadder U1(top1a,top1b,top1s,top1c);
endmodule

module top2(top2p,top2q,top2ci,top2co,top2sum);//修改全加器模块参数的模块top2
input top2p,top2q,top2ci;
output top2co,top2sum;
defparam U2.U1.xor_delay = 6,//名为U2的全加器实例中引用的名为U2的半加器实例中对参数xor_delay和and_delay的修改
		U2.U2.and_delay = 7;
		U2.or_delay = 5;//名为U2的全加器实例中对参数or_delay值修改
fulladder U2(top2p,top2q,top2ci,top2co,top2sum);
endmodule

3.2 Gate-level modeling

(1) Types of Verilog HDL basic gate-level components
Verilog HDL has 26 built-in basic components, of which 14 are gate-level components and 12 are switch-level components. The 26 basic components and their classification are shown in the table below.

type		element
basic door	multi-input gate	and, nand, or, nor, xor, xnor
	multi-input gate	buf, not
Three-state gate	Allows defining drive strength	buif0, bfif1, notif0, notif1
mos switch	no drive strength	nmos, pmos, cmos, rnmos, rpmos, rcmos
two-way switch	no drive strength	tran,tranif0,tranif1
	no drive strength	rtran, rtranif0, rtranif1
上拉，下拉电阻	允许定义驱动强度	pullup, pulldown

Verilog中丰富的门级元件为电路的门级结构提供了方便。Verilog语言中的门级元件见下表:

（2）门级模块调用
多输入门元件调用的语法格式是：
门类型 <实例名>(<输出端口1>, <输出端口2>, ..., <输出端口n>, <输入端口>);
例如：

多输出门元件调用的语法格式是：
元件名 <实例名>(<输出端口1>, <输出端口2>, ..., <输出端口n>, <输入端口>);
例如：

三态门元件调用的语法格式是：
元件名 <实例名>(<数据输出端口>, <数据输入端口>, <控制输入端口>);
例如：

例如：调用门级元件实现下图2-4译码管

3.3 开关级建模

Verilog语言提供了十几种开关级基元，它们是实际的MOS管的抽象表示。这些开关级基元分为两大类：一类是MOS开关，一类是双向开关。每一大类又可分为电阻型（前缀用r表示）和非电阻型。
（1）MOS开关
MOS开关模拟了实际的MOS器件的功能，包括nmos、pmos、cmos 三种。
nmos和pmos的实例化语格式是：
nmos或pmos 实例名(out, data, control);
coms开关的实例化语言格式是：
cmos 实例名(out, data, ncontrol, pcontrol);
(2)双向开关
MOS开关只提供了信号的单向驱动能力，为了模拟实际的具有双向驱动能力的门级开关，Verilog语言提供了双向开关。双向开关的每个脚都被声明为inout类型，都可以作为输入驱动另一脚，也可以作为输出被另一脚驱动。
双向开关包括无条件双向开关(tran)和有条件双向开关(tranif0、 tranifl）。
无条件双向开关的例化语言格式是：
tran 实例名(inout1，inout2);
有条件双向开关示例化语言格式是：
tranif0或tranif1 实例名(inoutl，inout2, control);

下表列出Verilog语言中提供的开关级元件和功能说明。

例如，基本的nmos开关电路

Source: Teacher Cai Jueping's Verilog course