Verilog study notes basic grammar (4) block statement

http://www.cnblogs.com/SYoong/archive/2016/09/08/5852128.html


A block statement refers to the grouping of two or more statements together to make it more like a single statement in format. There are two types of block statements:

1) Use the begin_end statement, which is usually used to identify the statement executed in sequence, and the block identified by it is called the sequence block;

2) Use the fork_join statement, which is usually used to identify the statement executed in parallel, and the block identified by it is called a parallel block.

 

A) Sequential block

begin

    statement 1;

    statement 2;

   ....

    statement n;

end

begin: block name

    statement inside block

    statement 1;

    statement 2;

   ....

    statement n;

end

Features:

1) The statements in the block are executed in order, that is, only the following statements can be executed after the execution of the above statement;

2) The delay time of each statement is relative to the simulation time of the previous statement;

3) Until the last statement is executed, the program flow control will not jump out of the statement block.

Within a begin-end statement block, begin-end and fork-join blocks can be nested within each other or themselves. If begin-end contains a local declaration, it must be named (must have a flag). If a begin-end block is to be prohibited, the prohibited begin-end must have a name.

 

B) Parallel Blocks

fork

    statement 1;

    statement 2;

   ....

    statement n;

join

fork: block name

    statement inside block

    statement 1;

    statement 2;

   ....

    statement n;

join

Features:

1) The statements in the block are executed at the same time, that is, when the program flow control enters the block, the statements in the block start to be executed in parallel at the same time;

2) The delay time of each statement in the block is relative to the moment when the program flow enters the block.

3) The delay time is used to provide the execution timing for the assignment statement;

4) When the execution of the last statement is sorted by time, or when a disable statement is executed, the program flow control jumps out of this module.

 

block name:

1) Local variables can be defined within the block, that is, variables that are only used within the block;

2) It can be allowed to be called by other statements, or it can be called by hierarchical name ;

3) In Verilog, all variables are static, that is, all variables have only one unique storage address, so entering or jumping out of a block does not affect the value stored in the variable.

4)命令块可以被禁用,关键词为disable,可以用disable跳出循环,处理错误条件以及根据控制信号来控制某些代码是否执行。

顺序块和并行块的性质对比

对比性质 顺序块 并行块
块内声明语句变量类型 parameter、reg、integer、real parameter、reg、integer、real、time、event
开始时间 第一条语句开始执行的时间 流程控制进入该块的时间
结束时间 最后一条语句结束执行时间 按时间排在最后的语句执行结束时间

 

 

 

 

 

举例:(程序功能相同的顺序块和并行块)

parameter  d=50;

reg   [7:0] r;

begin

    #d   r='h35;

    #d   r='hE2;

    #d   r='h00;

    #d   r='hF7;

    #d   ->end_wave;                   //->表示触发事件end_wave使其翻转

end

 (如果d=0,则这个顺序块的执行不需要时间。若d=50,则块语句完成的时间为250,因为每个语句都要等待50个时间单位)

fork

    #250  ->end_wave; 

    #200   r='hF7;

    #150   r='h00;

    #100   r='hE2;

    #50     r='h35;

join

(在并行块中,所有语句都是在程序流程进入并行块时同时开始的,因此这个语句结束的时间为250)

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