Good in Verilog model of logic gates and the switch has been some build. In the modules involved in the switching doors can be referenced model by way of example, the module thus structured will be described.
Logic gates:
and (output,input,...)
nand (output,input,...)
or (output,input,...)
nor (output,input,...)
xor (output,input,...)
xnor (output,input,...)
Buffers and NAND gate
buf (output,...,input)
not (output,...,input)
Tri-state gate:
bufif0 (output,input,enable)
bufif1 (output,input,enable)
notif0 (output,input,enable)
notif1 (output,input,enable)
MOS switch
nmos (output,input,enable)
pmos (output,input,enable)
rnmos (output,input,enable)
rpmos (output,input,enable)
CMOS switch
cmos (output,input,Nenable,Penable)
rcmos (output,input,Nenable,Penable)
Two-way switch:
tran (inout,inout2)
rtran (inout,inout2)
Way controllable switch
tranif0 (inout1,inout2,control)
tranif1 (inout1,inout2,control)
rtranif0 (inout1,inout2,control)
rtranif1 (inout1,inout2,control)
Pull-up and pull-down source the source
pullup (output)
pulldown (output)
The following is a truth table of the gate circuit:
Wherein the logic values of L and H represents the unknown value portion. L represents 0 or Z, H represents the Z or 1;
Schedule 1 to the AND gate truth table
and
0
1
x
with
0
0
0
0
0
1
0
1
x
x
x
0
x
x
x
with
0
x
x
x
Schedule 2 to the NAND gate truth table
nand
0
1
x
with
0
1
1
1
1
1
1
0
x
x
x
1
x
x
x
with
1
x
x
x
Schedule 3 or gate truth table
or
0
1
x
with
0
0
1
x
x
1
1
1
1
1
x
x
1
x
x
with
x
1
x
x
NOR gate truth table Table 4
nor
0
1
x
with
0
1
0
x
x
1
0
0
0
0
x
x
0
x
x
with
x
0
x
x
XOR gate truth table Table 5
xor
0
1
x
with
0
0
1
x
x
1
1
0
x
x
x
x
x
x
x
with
x
x
x
x
NOR gate truth table of Schedule 6
xor
0
1
x
with
0
1
0
x
x
1
0
1
x
x
x
x
x
x
x
with
x
x
x
x
Schedule 7 buffer and the NAND gate truth table
buf
not
Input
Output
Input
Output
0
0
0
1
1
1
1
0
x
x
x
x
with
x
with
x
Table 8 Truth Table buffer enable terminal
Bufif0
Enable
Bufif1
Enable
0
1
x
with
0
1
x
with
D
A
T
A
0
0
with
L
L
D
A
T
A
0
with
0
L
L
1
1
with
H
H
1
with
1
H
H
x
x
with
x
x
x
with
x
x
x
with
x
with
x
x
with
with
x
x
x
Table 9 buffer enable terminal of the NAND gate truth table
notif0
Enable
notif1
Enable
0
1
x
with
0
1
x
with
D
A
T
A
0
1
with
H
H
D
A
T
A
0
with
1
H
H
1
0
with
L
L
1
with
0
L
L
x
x
with
x
x
x
with
x
x
x
with
x
with
x
x
with
with
x
x
x
Schedule control terminal 10 MOS-type truth table
Pmos
Rpmos
Control
Nmos
Rnmos
Control
0
1
x
with
0
1
x
with
D
A
T
A
0
0
with
L
L
D
A
T
A
0
with
0
L
L
1
1
with
H
H
1
with
1
H
H
x
x
with
x
x
x
with
x
x
x
with
with
with
with
with
with
with
with
with
with
rule:
1) buffer gate, a NOT gate can have a plurality of output, these output values are the same.
2) When the nmos, pmos, cmos, tran, tranif0, tranif1 type switch is turned on, it does not change its signal strength from input to output.
3) when the resistor switch, such as rnmos, rpmos, rcmos, rtran, rtranif0, rtranif1 types of switches, open type, can change its output signal from the input to the intensity.
Strength
Reduced
supply
pull
strong
pull
pull
weak
large
medium
weak
medium
medium
small
small
small
highz
highz
---------------------
Author: SYoong
Source: CNBLOGS
Original: https://www.cnblogs.com/SYoong/p/6068439.html
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