Verilog Programming - Event/Pulse Fusion

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introduction

Let's record another question about Haikang's internship machine test this year, which is relatively simple. Concerning the fusion of multiple impulsive signals arriving at different times.

topic description

eof indicates the end pulse of one event. In order to indicate that two events of uncertain order have ended, the two end pulses need to be fused to output one pulse, and the following code should be cleared and improved: 

module event_merge(
input 				clk,
input 				rst_n,
input 				eof1,//脉冲信号，时长：1个clock
input 				eof2,//脉冲信号，时长：1个clock
output wire 		eof
    );

train of thought

The simplest idea is to count the pulses. Of course, the simultaneous arrival of event pulses should also be considered to avoid bugs. If you have other ideas, welcome to exchange in the comment area~~

problem solving

Design code:

// ========================================================================
// 功能描述：-1- 将两个事件脉冲融合为1个脉冲
// 作者：Xu Y. B.
// 时间：2023-05-08
// ========================================================================

`timescale 1ns / 1ps
module event_merge(
input 				clk,
input 				rst_n,
input 				eof1,//脉冲信号，时长：1个clock
input 				eof2,//脉冲信号，时长：1个clock
output wire 		eof
    );

reg [1:0] count;

always @ (posedge clk)
begin
	if(~rst_n)
	begin
		count <= 0;
	end
	else if(count == 2)
	begin
		count <= 0;
	end
	else if(&{eof1,eof2})
	begin
		count <= 2;
	end
	else if(|{eof1,eof2})
	begin
		count <= count + 1;
	end
end

assign eof = count == 2;
endmodule

Simulation code:

// ========================================================================
// 功能描述：-1- 仿真测试模块 event_merge 功能
// 作者：Xu Y. B.
// 时间：2023-05-08
// ========================================================================

`timescale 1ns / 1ps
module tb_event_merge();

reg 				clk;
reg 				rst_n;
reg 				eof1;//脉冲信号，时长：1个clock
reg 				eof2;//脉冲信号，时长：1个clock
wire 				eof;

initial clk = 0;
always #10 clk = ~clk;

initial
begin
	rst_n = 0;
	eof1 = 0;
	eof2 = 0;
	#103;
	@(posedge clk)
	rst_n <= 1'b1;

// case1  :  eof2 先到来 ，eof1 后到来 
	#1034;
	@(posedge clk)
	eof2 <= 1'b1;
	@(posedge clk)
	eof2 <= 1'b0;
	#2098;
	@(posedge clk)
	eof1 <= 1'b1;
	@(posedge clk)
	eof1 <= 1'b0;

// case2  :  eof1 先到来 ，eof2 后到来 
	#1034;
	@(posedge clk)
	eof1 <= 1'b1;
	@(posedge clk)
	eof1 <= 1'b0;
	#2098;
	@(posedge clk)
	eof2 <= 1'b1;
	@(posedge clk)
	eof2 <= 1'b0;

// case3  :  eof1 ，eof2 同时到来 
	#1034;
	@(posedge clk)
	eof1 <= 1'b1;
	eof2 <= 1'b1;
	@(posedge clk)
	eof1 <= 1'b0;
	eof2 <= 1'b0;
	#2309;
	$finish;
end

event_merge INST_event_merge (.clk(clk), .rst_n(rst_n), .eof1(eof1), .eof2(eof2), .eof(eof));

endmodule

Simulation results:

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