Getting Started with Verilog (2) (Verilog Language Elements)

identifier

The identifier in Verilog HDL can be any set ofletters,digits< A combination of the /span> (underscore) symbol, but the first character of the identifier must be a letter or underscore. Additionally, identifiers are case-sensitive. $ symbols and the , _

An escaped identifier can contain any printable character in an identifier. Escaped identifiers start with a \ (backslash) symbol and end with a whitespace.

Verilog HDL defines a series of reserved words, called keywords, which are used only in certain contexts. Note that only lowercase keywords are reserved words. For example, the identifier always (which is a keyword) is different from the identifier ALWAYS (which is not a keyword).

Comment

There are two forms of comments in Verilog HDL.

/* 第一种形式：可以扩展至
   多行 */

// 第二张形式：在本行结束。

Format

Verilog HDL is case-sensitive. In other words, identifiers with different upper and lower case are different. Furthermore, Verilog HDL is free-form, i.e. structures can be written across multiple lines or within a single line.

For example

initial begin Top=3'b001; #2 Top=3'b011; end

Same as the following command:

initial
  begin
    Top = 3'b001;
    #2 Top = 3'b011;
  end

System tasks and functions

Identifiers starting with $ characters represent system tasks or system functions. Tasks provide a mechanism for encapsulating behavior. This mechanism can be invoked in different parts of the design. Tasks can return 0 or more values. A function is the same as a task except that it can only return one value. In addition, functions are executed at time 0, that is, no delays are allowed, while tasks can have delays.

$display("Hi, you have reached LT today");
/* $display 系统任务在新的一行中显示。 */
$time
// 该系统任务返回当前的模拟时间

value set

Verilog HDL has the following four basic values:

1. 0: logical 0 or "false"
2. 1: logical 1 or "true"
3. x: unknown
4. z: high resistance

Note that the interpretation of these four values ​​is built into the language. For example, a value of z always means high impedance, and a value of 0 usually means logic 0. Constants in Verilog HDL are composed of the above four types of basic values.
There are three types of constants in Verilog HDL:

1. integer
2. real number type
3. string type

The underscore symbol _ can be used arbitrarily with integers or real numbers; they have no meaning in terms of quantities. They can be used to improve readability; the only restriction is that the underscore character cannot be used as the first character.

type of data

Verilog HDL has two main categories of data types.

1. Network type. . net type represents the physical connection between Verilog structured components. Its value is determined by the value of the driving element, such as a continuous assignment or the output of a gate. If no drive element is connected to the net, the net's default value is z.
2. Register type. register type represents an abstract data storage unit, which can only be assigned in the always statement and initial statement, and its value is assigned from one to the other. be preserved.

parameter

The parameter is a constant. Parameters are often used to define delays and variable widths. Parameters specified using parameter specifications are assigned only once. The parameter description form is as follows:

parameter param1 = const_expr1, param2 = const_expr2, ...,
          paramN = const_exprN;

The following are specific examples:

parameter LINELENGTH = 132, ALL_X_S = 16'bx;
parameter BIT = 1, BYTE = 8, PI = 3.14;
parameter STROBE_DELAY = (BYTE + BIT) / 2;
parameter TQ_FILE = " /home/bhasker/TEST/add.tq"