[FPGA] IIC read and write EEPROM

- IIC protocol

1.1 iic introduction

I2C stands for Inter-Integrated Circuit (Integrated Circuit Bus), developed by Philips Semiconductor Corporation (now NXP

A simple, two-way, two-wire bus standard designed by Semiconductor Corporation in the early 1980s. Multi-purpose for master and slave

Master-slave communication where the amount of data is not large and the transmission distance is short. The host starts the bus and generates clocks for data transfer,

Any device receiving data at this point is considered a slave.

IIC is a two-wire serial bus, which consists of a data line SDA and a clock line SCL to form a communication line, which can be used to send data or receive data. It is a half-duplex communication protocol. Two-way data transmission is performed between the master device and the slave device on the bus in units of bytes. It is mostly used for master-slave communication between the master and the slave in the case of small data volume and short transmission distance.

The I2C bus consists of a data line SDA and a clock line SCL to form a communication line, which can be used to send data or receive data. exist

Two-way data transmission can be performed between the master control and the controlled IC, and the data transmission rate can reach 100kbit/s in standard mode, and in fast

It can reach 400kbit/s in high-speed mode and 3.4Mbit/s in high-speed mode. Various controlled devices are connected in parallel on the bus.

Device address (SLAVE ADDR, for details, please refer to the device manual) identification.

1.2 iic transfer rate

Standard: 100kbit/s,

Fast: 400kbit/s,

High speed: 3.4Mbit/s.

In the experiment of reading and writing EEPROM, the rate is (50Mbit/s)/250=200Kbit/s

1.3 iic features (physical layer)

(1) It is a bus that supports multiple devices (supports multiple masters and multiple slaves).

(2) The IIC bus uses only two bus lines, a bidirectional serial data line (SDA) and a serial clock line (SCL). The data line is used to represent data, and the clock line is used to synchronize data transmission and reception.

(3) Each device connected to the IIC bus has an independent address, and the host can use the device independent address to access different devices.

(4) The IIC bus is connected to the power supply through a pull-up resistor. When the IIC device is idle, the device will output a high-impedance state. When all devices are idle and output a high-impedance state, the pull-up resistor pulls the IIC bus to a high level.

(5) The IIC bus has an arbitration mechanism.

1.4 iic timing

Idle state:
When the two signal lines SDA and SCL of the I2C bus are at high level at the same time, it is defined as the idle state of the bus. At this time, the output stage field effect transistors of each device are in the cut-off state, that is, the bus is released, and the level is pulled high by the pull-up resistors of the two signal lines.

Start signal:
generated by the host, when SCL is kept high, the level of SDA is pulled low, which is called the start signal of the I2C bus, which marks the start of a data transmission. The start signal is actively established by the host, and the I2C bus must be in an idle state before the signal is established.

Data transmission:
serially transmit data in units of bytes , each transmission of 1bit data requires a clock cycle, that is, 20 * 250ns, transmit data when the clock line is at low level, and remain unchanged at high level , for sampling. When the clock signal line SCL is at low level, the data to be written is given to the data signal line SDA in advance, so that when the clock signal line SCL is at high level, the data on the data signal line SDA can be accurately obtained.

When sda and scl are at low level, the sender starts to send data. When the 8bit data is received, a response signal ACK will be fed back through the data line . The response signal is active at low level, indicating that the byte has been received; when the feedback is at high level Usually, it means that the byte has failed to be received. During the feedback period, that is, the receiving end pulls SDA low before the ninth clock pulse to ensure that it remains low during this clock cycle. In addition, sending multi-byte data will continue to send data during the low-level period of scl after the effective response. When all byte data is sent, a NACK high-level is fed back, and sampling is performed during the high-level period of scl. At this time, the sending data is completed. Finish sending. into the stop position.

Response signal:
All data on the 12C bus is transmitted in bytes. When the sending end sends a byte, it must release SDA during the ninth SCL pulse, and the receiving end will feed back a response signal. When the response signal is at a low level, it is called an effective response bit (ACK), indicating that the receiving end has successfully received the byte; when the response signal is at a high level, it is called a non-acknowledgment bit (NACK), indicating that the receiving end has failed to receive the byte . The requirement for feeding back the effective acknowledgment bit ACK is that the receiving end pulls SDA low during the low level period before the ninth clock pulse, and ensures that it remains low during the high level period of the clock cycle. If the receiving end is the master control end, after it receives the last byte, it sends a NACK signal to notify the controlled sender end to end data transmission, and releases the SDA line so that the master control receiver sends a stop signal.

Stop signal:
While SCL remains high, SDA is released and returns high, which is called the stop signal of the I2C bus, marking the termination of a data transmission. The stop signal is actively established by the host. After the signal is established, the I2C bus will return to the idle state.

Two SCCB agreement

2.1 Introduction to SCCB

SCCB (Serial Camera Control Bus) is a serial camera control bus protocol announced by OmniVision, which is equivalent to a simple I2C protocol. SCCB can be divided into three-wire and two-wire, the three-wire is one master and multiple slaves, and the two-wire is one master and one slave.

2.2 Data transmission

In the SCCB protocol, a basic transmission unit is called a phase (phase), a phase contains a total of 9 bits, the first 8 bits are data, and its response signal ACK is called the ninth bit of a transmission unit, which is divided into Don' t care and NA (No ACK). The Don't care bit is generated by the slave; the NA bit is generated by the master. Since the SCCB does not support multi-byte reading and writing, the NA bit must be high. sCCB does not have the concept of repeated start, so in the read cycle of SCCB, after the master sends the on-chip register address, it must send a bus stop condition. Otherwise, the slave will not be able to generate a Don't care response signal when sending a read command.
When writing data to the slave is defined as a write transfer, when reading data from the slave is defined as a read transfer, each transfer must have a start bit (start) and an end bit (sotp); a complete data transfer includes two or Three stages, each stage contains 9 bits of data, among which the upper 8 bits are the data to be transmitted, and the lowest bit has different values according to the read and write conditions of the device: Each stage consists of: 8 bits of data + don't care/
NA
If the master sends data, that is, a write operation, the ninth bit is don't care; if the slave sends data, it is a read operation, and the ninth bit is NA.

dont care:
the camera sends data to the host, don't care about sending 0 or 1,
NA:
the host sends a stop bit to the slave, sda is high

2.3 Write operation

Three-phase write transfer or four-phase write

ID Addr : Indicates the device address of the slave and a read-write control bit 7-bit device address + 1 write control bit 0

Sub Addr : Indicates the register address of the slave

Write Data : One byte of data written by the master to the slave

X : slave feedback don't care, don't care about 0 or 1

Special attention : the device address of the ov5640 camera has two bytes, so the write operation is a four-phase write transmission, first start bit + device address + byte high address + byte byte + one byte data

2.4 Read operation

The read operation is divided into two phases:

The first stage:

Write: two-phase write transfer or three-phase write

ID Addr : Indicates the device address of the slave and a read-write control bit 7-bit device address + 1 write control bit 0

Sub Addr : Indicates the register address of the slave

X : slave feedback don't care, don't care about 0 or 1

second stage:

ID Addr : Indicates the device address of the slave and a read-write control bit 7-bit device address + 1-bit read control bit 1

Read Data : Eight bits of data sent from the slave to the host

X : slave feedback don't care, don't care about 0 or 1

NA : The master responds to the data sent by the slave, which is high

Three EEPROMs

3.1 Write Operation Timing

Write operation, send start bit -> write control word -> receive ACK -> write byte address -> receive ACK -> write data receive ACK -> send stop bit.
Write control word:
{7'b101000,1'b0}

Single byte write : write only one byte at a time.

Page write : 16 bytes can be written at a time.

3.2 Read Operation Timing

Read from current address :
send start bit -> write control word -> receive ACK -> write read address -> receive read data -> send NACK -> send stop bit.

Random read :
random read, send start bit -> write control word -> write read address -> receive ACK -> send start bit -> write read control word -> receive read data -> send NACK -> send stop bit.

Sequential read :
sequential read, send start bit -> write control word -> write read address -> receive ACK -> send start bit -> write read control word -> receive read data -> send ACK -> receive read data -> Send NACK -> send stop bit.