AXI bus bandwidth test

Code 1

void hp_test(volatile int* a1,volatile int* b){
    
    
#pragma HLS INTERFACE m_axi port=a1 offset=slave bundle=IN1
#pragma HLS INTERFACE m_axi port=b offset=slave bundle=OUT
#pragma HLS INTERFACE s_axilite port=return bundle=CTRL
	int buff[10000];
	int i;
	loop1:for(i=0;i<10000;i+=4){
    
    
		buff[i]=*(a1+i);
		buff[i+1]=*(a1+i+1);
		buff[i+2]=*(a1+i+2);
		buff[i+3]=*(a1+i+3);
	}

	loop2:for(i=0;i<10000;i++)
		*(b+i)=buff[i];
}

Code 2

Code 2 has two connection methods, four IN ports are connected to only one AXI HP port, and four IN ports are connected to four AXI HP ports respectively.

The final experimental results are as follows:
Code 1: 1 AXI interface takes 1378us
Code 2: 4 AXI interfaces 1 AXI HP interface takes 619us
Code 2: 4 AXI interfaces 4 AXI HP interface takes 511us
visible even if multiple AXI interfaces are connected 1 One HP interface can also increase bandwidth, while multiple AXI HP interfaces can achieve greater bandwidth.