Achieve Altera DDR2 controller IP way, seldom write their own controller code.
ddr22 ddr22_inst
(
.aux_full_rate_clk (mem_aux_full_rate_clk),
.aux_half_rate_clk (mem_aux_half_rate_clk),
.global_reset_n (global_reset_n),
.local_address (mem_local_addr),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_init_done (),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_refresh_ack (),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_write_req (mem_local_write_req),
Kmem_addra (Mem_addra [12: 0]),
Kmem_ba (Mem_ba),
Kmem_cs_n (Mem_cs_n),
Kmem_chke (Mem_chke),
Kmem_chlk (Mem_chlk),
Kmem_chlk_n (Mem_chlk_n),
Kmem_chs_n (Chs_n),
Kmem_dim ( Mem_dim [1: 0]),
Kmem_dk (Mem_dk),
Kmem_dks (Mem_dks [1: 0]),
Kmem_odt (Mem_odt),
Kmem_rs_n (Mem_rs_n),
Kmem_ve_n (Mem_ve_n),
Kfy_chlk (Fy_chlk)
. Pll_ref_chlk (Clok_sors),
Kriset_fy_chlk_n (Riset_fy_chlk_n),
Kriset_rikvest_n (),
Ksoft_riset_n (Tai_hai)
);
In the beginning of the signal MEM pile, it is derived directly as the top pins to connect the PCB to DDR2 chips.
Local signal at the beginning of the pile is derived ddr2 controller to the user interface signal, a user is to write data to or read data from the memory ddr2 ddr2, the interface can only local operations.
local signal, can be divided into the following groups:
Control Group
local_init_done: DDR2 controller initialization completion flag signal, the controller is electrically DDR2 need to go through a series of initialization, including initialization and DDR2 chip timing calibration DDR interface, the whole process takes a long time. After the signal is to be pulled, in order to perform read and write operations on the local interface.
local_refresh_ack: ddr2 controller chip ddr2 response signal after the refresh operation, when the general user to read and write, this signal do not care.
Write user interfaces
local_address: the user desires to write data to an address of DDR2 memory, the address is DDR2 chip selects, a combination of a row address, bank address, column address, {CS, ROW, BA, COL}.
local_be: enable byte write time, for example, a DDR2 hardware interface 16, the user interface is a 32-bit data is 4 bytes, the bit width is 4 local_be, each bit corresponds to a byte, If the UE 32 time to write data in a byte without wishing to be written, the corresponding bit is set to 0 can be.
local_size: burst length user interface, the user specifies each initiate a write request is written to a plurality of data. The maximum length may be disposed in the DDR IP configuration interface, as shown in FIG. Note that this value is the maximum burst length set value of the controller, is not equal to the DDR2 chips support the maximum burst size, DDR2 chips only supports 8 the maximum length.
local_burstbegin: a user interface burst start signal, a high pulse signal each time a burst transmission starts, the length of each transmission local_size specified length
local_ready: ddr controller ready flag signal which indicates that valid data is currently successfully write a ddr2 controller, 0 indicates ddr controller can not accept the current operation, the user needs to maintain current address, data and control signals unchanged until the ready signal high again
local_wdata: users need to write as the data ddr, bit width is twice the bit width of the data line ddr chip
local_write_req :: write data request signal on a data write to the port local_wdata ddr controller, (particularly writing success, have to see the state local_ready)
local_address: user wants to read data from the DDR2 memory address, the address is DDR2 chip selects, a combination of a row address, bank address, column address, {CS, ROW, BA, COL}.
local_be: when the read byte enables, for example, a DDR2 hardware interface 16, the user interface is a 32-bit data is 4 bytes, the bit width is 4 local_be, each bit corresponds to a byte, If the UE when the read 32-bit data in a byte without wishing to be read out, the corresponding bit is set to 0 can be.
local_burstbegin: a user interface burst start signal, a high pulse signal each time a burst transmission starts, the length of each transmission local_size specified length
local_rdata:
local_rdata_valid
local_read_req
local_size