PCIE obtained by the earlier derived and PCI expansion of PCI compatible, have two main difference is that a parallel to serial switch have, and at a faster rate. Currently on the board was more and more devices are mounted next to the PCI bus, and even some hard disk will mount the PCI bus below, PCIE have seen more and more widely. PCIE design and broad range of knowledge, are very important both in under BIOS or system. This chapter introduces the basic concepts of PCIE and basic literacy, students learn first must-see.
Knowledge literacy:
1. usually see x1, x2, x4, x8, x16, x32, how to understand?
X1 represents a Lan, PCIE bus go difference signal, a line may receive Lan4 may be transmitted. Similarly, x2 represents 2 Lan, and so on, more Lan number, the faster the data transfer. Multiple channels can also be combined into x1, x2, x4, x12, x16, x32, to increase the available bandwidth of the slot
2. Under normal circumstances:
PCI-Express X1 / X2 / X4, supported by south bridge
PCI-Express x8 / x16, supported by Northbridge
x1 / x2 is mainly used to expand sound cards, network low-speed device for elimination PCI slot
x4 card is used to expand the array devices like speed, for PCI-X slots out
x8 / x16 expansion card is used to tell the device such as, for out of the AGP slot
3 on South Bridge
North Bridge to mount a number of multi-speed devices, such as video card, memory. Southbridge multi-mount low-speed devices such as LPC interface, network cards, etc.
due to the North Bridge chip is integrated within the multi-CPU, Southbridge across Taking a look at their brothers gone, it is not good then told Southbridge, plus Intel processor modules more integrated, so PCH was born. Southbridge PCH or as main functions, including ICHICH (I / O controller hub input-output controller hub) links responsible for the PCI bus, the IDE devices, I / O devices.
Note: PCH is also present on the motherboard on a single chip, the chip is connected between the CPU via DMI interface, mostly in the South Bridge as the LPC interfaces, ports, etc. PCIE part will be exposed on the PCH chip, without storm drain on the CPU processor. PCH is currently part of Intel processors will also be integrated on the CPU SOC, more integrated, all pins are exposed on the CPU SOC. (PCH previous landlord has to do not understand, others say Reference Manual, which is part of PCH, it is part of the CPU, and made a little dizzy, it can simply understood as the two chips)
4. About communication PCIE
PCIE is described earlier is a basic Lan communication units transmit data via a set of differential signals. A receiving a hair, half-duplex communication mode, may be set to full duplex communication mode!
To be completed unfinished <<<