Foreword
This article mainly introduces the hardware interface resources and design considerations of the TL64x-EVM evaluation board.
Chuanglong Technology TL64x-EVM is a high-performance evaluation board based on TI Sitara series AM64x dual-core ARM Cortex-A53 + single/quad-core Cortex-R5F + single-core Cortex-M4F multi-core processor design. It consists of a core board and an evaluation board . The core board has been verified by professional PCB layout and high and low temperature tests, high performance and low power consumption, stable and reliable, and can meet various industrial application environments.
The evaluation board is rich in interface resources, leading to 5x Ethernet (two channels support TSN), 2x CAN-FD, multi-channel UART, multiple DI/DO, GPMC, PCIe, USB and other interfaces, onboard WIFI module, supports 4G/5G modules, NVME hard disk, the optional shell can be directly applied to the industrial site, which is convenient for users to quickly conduct product solution evaluation and technology pre-research.
The IO level standard of AM64x is generally 1.8V or 3.3V, and the pull-up power supply generally does not exceed 3.3V. When the external signal level does not match the IO level, a level conversion chip or a signal isolation chip needs to be added in the middle. ESD design needs to be considered for buttons or interfaces. When selecting ESD devices, attention should be paid to whether the junction capacitance is too large, otherwise it may affect signal communication.
Figure 1 Evaluation board hardware resource diagram 1
Figure 2 Evaluation board hardware resource diagram 2
1 SOM-TL64x core board
The SOM-TL64x core board is equipped with CPU, ROM, RAM, crystal oscillator, power supply, LED and other hardware resources, and leads out IO through B2B connection. For detailed content such as core board hardware resources, pin descriptions, electrical characteristics, mechanical dimensions, and backplane design considerations, please refer to the "SOM-TL64x Core Board Hardware Manual".
Figure 3 Core board hardware block diagram
Figure 4
Figure 5
2 B2B connectors
The evaluation board adopts 4 industrial-grade B2B connectors from Lianke Company, with a total of 240 pins, a pitch of 0.5mm, and a combined height of 4.0mm. Two 60pin female B2B connectors (CON0A, CON0B), model NLWBS05-60C-3.0H, height 3.0mm; two 60pin male B2B connectors (CON0C, CON0D), model NLWBP05-60C-1.0H, height 1.0mm.
Figure 6
3 power connector
CON1 is the 12V DC input green terminal, 3pin specification, 3.81mm pitch. CON2 is a 12V DC input DC-005 power interface, which can be adapted to a power plug with an outer diameter of 5.5mm and an inner diameter of 2.1mm. The power input has reverse polarity protection, overcurrent and overvoltage protection functions.
SW1 is a power toggle switch.
Figure 7
Figure 8
Design Considerations:
(1) VDD_12V_MAIN outputs VDD_5V_MAIN through the DC-DC step-down chip for the core board and some peripherals on the evaluation board, and outputs VDD_3V3_MAIN through another DC-DC step-down chip for the peripherals on the evaluation board. VDD_3V3_MAIN outputs VDD_1V8 through the LDO chip for the peripherals on the evaluation board.
Figure 9
Figure 10
Figure 11
(2) In order to make VDD_3V3_MAIN, VDD_1V8 and other power supplies meet the system power-on and power-off sequence requirements, it is recommended to refer to the following circuit for power enable design.
Figure 12
(3) VDD_5V_MAIN does not reserve a large energy storage capacitor for the total power input inside the core board. Please place a large energy storage capacitor near the pad of the B2B connector when designing the backplane.
4 LED
The evaluation base board has a total of 6 LEDs, LED0, LED1, LED2, LED3, LED4, LED13. LED0 is the power indicator light, which is on by default after power-on; LED1, LED2, and LED3 are user-programmable indicators, which are controlled by GPIO and are lit at a high level by default; LED4 is the 4G/5G module status indicator; LED13 is the NVMe solid-state drive /5G module expansion interface (CON17) indicator.
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
5 JTAG interface
CON5 is a TI Rev B JTAG emulation debugging interface. It adopts a 14pin simple socket connector with a pitch of 2.54mm. It can be adapted to the TL-XDS100V2, TL-XDS200 and TL-XDS560V2 emulators of Chuanglong Technology.
Figure 19
Figure 20
Design Considerations:
(1) When designing the backplane, if the JTAG bus only leads to test points and is connected to the emulator through flying leads, it is necessary to connect the TDIS pin of the emulator to the digital ground of the backplane to prevent the emulator from being unable to recognize the device normally.
6 BOOT SET Start mode selection DIP switch
SW2 is a 6bit start mode selection dial switch. There are three commonly used start-up modes as follows. Please determine the start-up mode according to the silkscreen on the evaluation board and select the position of the DIP switch.
(1) SD MMC1 mode: 101000(1~6)
(2) eMMC MMC0 mode: 001001(1~6)
(3) QSPI NOR mode: 010010(1~6)
Figure 21
The core board has directly led out the BOOTMODE[0:15] pin. Among them, the BOOTMODE[3:6] and BOOTMODE[8:9] pins are connected to the BOOT SET boot mode selection dial switch on the evaluation board for selection of the evaluation board boot mode, and the remaining pins have been pulled up and down on the evaluation board.
Figure 22
Design Considerations:
(1) The BOOTMODE[0:15] pin uses the VDD_3V3_SOM_OUT dedicated configuration power output from the core board. Do not use VDD_3V3_SOM_OUT for power supply for other loads.
(2) Since the BOOTMODE[0:15] pins are multiplexed with the GPMC bus, if you need to use GPMC external devices, please ensure that the BOOTMODE[0:15] pin level is not affected by the external connection during the power-on initialization process of the CPU. device, so as not to cause the CPU to fail to start normally.
7 KEY
The evaluation base board contains 1 core board power reset button (KEY1), 1 SoC Warm Reset button (KEY2), 1 MCU Warm Reset button (KEY3), 2 user input buttons (KEY4) and (KEY5).
Figure 23
Figure 24
Figure 25
Design Considerations:
(1) <POR_IN>/PU/3V3 is the power-on reset input pin of the core board. The 10K resistor has been pulled up inside the core board. Please leave it floating by default.
(2) E18/<RESET_REQz>/PU/3V3 is the Warm Reset input pin of the CPU. The 100K resistor has been pulled up inside the core board. Please leave it floating by default.
(3) B12/<MCU_RESETz>/PU/3V3 is the Warm Reset input pin of the MCU domain. The 100K resistor has been pulled up inside the core board. Please leave it floating by default.
8 serial ports
The evaluation board has 9 serial ports, CON4 is USB TO UART0 serial port, CON8 is RS232 UART1 serial port, CON9 is MCU RS232 UART0 serial port, J17 contains RS485 UART3 and RS485 UART6 serial port, CON11 is TTL UART2 serial port, CON12 is TTL UART4 serial port, CON14 is TTL UART5 serial port, CON15 is MCU TTL UART1 serial port.
8.1 USB TO UART0 serial port
The evaluation board converts UART0 into a Micro USB interface through the CH340T chip, which is used as a system debugging serial port.
Figure 26
Figure 27
8.2 RS232 UART1/MCU RS232 UART0 serial port
The evaluation board converts UART1 and MCU UART0 into 2-way RS232 serial ports through 2 serial port level conversion chips SP3232EEY-L/TR (maximum communication rate is 235Kbps), using DB9 interface.
Figure 28
Figure 29
8.3 RS485 UART3/RS485 UART6 serial port
The evaluation board converts UART3 and UART6 into two RS485 serial ports through two isolated transceivers CA-ISO3082WX (maximum communication rate of 500Kbps), and shares the green terminal (J17) of 10pin specification and 3.81mm spacing with CAN1 and CAN2.
Figure 30
Figure 31
8.4 TTL UART2/TTL UART4/TTL UART5/MCU TTL UART1串口
UART2, UART4, UART5, and MCU UART1 directly lead to TTL level test pins through 4pin specification, 2.54mm pitch white pin header terminals.
Figure 32
Figure 33
There is a pin multiplexing relationship between UART4, UART5 and CAN, and the pin headers of J3, J4, J5, and J6 can be configured through jumper caps to flexibly select the corresponding functions.
Figure 34
9 CAN interface
The evaluation board leads CAN1 and CAN2 interfaces through two isolated transceivers NSI1050-DDBR (maximum communication rate is 1Mbps), and shares 10pin specification, 3.81mm pitch green terminal (J17) with RS485 UART3 and RS485 UART6.
Figure 35
Figure 36
10 Micro SD interface
CON6 is a Micro SD interface, which is led out through MMC1 and adopts 4bit data line mode.
Figure 37
Figure 38
Design Considerations:
(1) When designing the backplane, it is necessary to connect the SHIELD[1:4] pins of the TF socket shell to the digital ground.
11 External RTC socket
The evaluation board uses the DS1307ZM/TR chip to implement the external RTC function. CON3 is an RTC button battery holder, suitable for button batteries ML2032 (3V rechargeable), CR2032 (3V not rechargeable). When using a rechargeable battery, the jumper cap can be inserted into the J1 interface to realize charging. When using a non-rechargeable battery, please do not insert the jumper cap into the J1 interface.
Figure 39
Figure 40
12 Watchdog interface
U13 is an external hardware watchdog chip. J16 is the interface for configuring the Watchdog function. It adopts a 2.54mm pitch and 3pin pin arrangement. The Watchdog function can be enabled by configuring a jumper cap.
Figure 41
Figure 42
13 FAN interface
J2 is the radiator fan power interface (FAN), which adopts 2.54mm spacing, 3pin pin row terminal mode, and 12V power supply.
Figure 43
Figure 44
Design Considerations:
(1) Since the radiator fan interface does not support the speed regulation function, it is not recommended to use PWM mode to control the radiator fan switch circuit.
14 USB HOST interface
CON16 (USB0 HOST) is a USB 2.0 HOST interface, using a double-layer Type-A connector. The evaluation board expands the USB0 bus to 4 USB HOST buses through the USB HUB chip, and leads 2 of them to the USB0 HOST interface.
Figure 45
Figure 46
15 Ethernet interface
15.1 CPSW Gigabit Ethernet port
CON21 is a double-layer gigabit RJ45 connector, and the RJ45 connector has a built-in isolation transformer. The lower layer is ETH1 (RGMII1) Gigabit Ethernet port, and the upper layer is ETH2 (RGMII2) Gigabit Ethernet port.
Figure 47
ETH2 supports CPSW and PRG1 modes, and the default is CPSW mode. If you need to use PRG1 mode, please switch the jumper caps J7 and J8 on the evaluation board to PRG1 mode.
Note: This function is only for AM6442.
Figure 48
Figure 49 ETH1
Figure 50 ETH2
Design Considerations:
(1) The DVDDL and AVDDL pins of YT8521SH-CA are powered. It is recommended to refer to the DC-DC power supply scheme of our evaluation board.
Figure 51
(2) XTAL_I, XTAL_O pins are connected to 25MHz passive crystal oscillator. If you need to use a 25MHz active crystal oscillator, you can access it from the XTAL_I pin and leave the XTAL_O pin floating.
(3) The YT8521SH-CA chip is required to hold for 10ms after the power supply is stable, and then pull the reset signal high. It is recommended to refer to the reset circuit scheme of the evaluation board.
Figure 52
15.2 PRG Gigabit Ethernet port
CON22 is a double-layer gigabit RJ45 connector, and the RJ45 connector has a built-in isolation transformer. The lower layer is ETH3 (PRG0_RGMII1) Gigabit Ethernet port, and the upper layer is ETH4 (PRG0_RGMII2) Gigabit Ethernet port.
Figure 53
Figure 54 ETH3
Figure 55 ETH4
CON23 is an ETH5 (PRG1_RGMII1) Gigabit Ethernet port, which uses a single-layer RJ45 connector and has a built-in isolation transformer.
Figure 56 ETH5
Design Considerations:
(1) It is recommended to use our evaluation board DCDC (SY8088IAAC) solution for the power supply of VDD1P0 and VDDA2P5 pins in DP83867IRRGZ.
Figure 57
(2) Connect XI and XO pins of DP83867IRRGZ to 25MHz passive crystal oscillator. If you need to use a 25MHz active crystal oscillator, you can access it from the XI pin, and leave the XO pin floating.
(3) It is recommended to design the reset circuit of DP83867IRRGZ by referring to the reset circuit scheme of the evaluation board.
16 NVMe SSD/5G module expansion interface
CON17 is an expansion interface for NVMe SSD/5G module. It adopts M.2 B Key slot, PCIe Gen2 standard, and the maximum communication rate is 5Gbps. It is used as PCIe RC (Root Complex) by default. Compatible with Quectel RM500Q-GL 5G module and M.2 B Key interface type NVMe solid state drive.
Note: When using a plastic crowbar to remove the core board, do not use the M.2 B Key slot as a fulcrum, otherwise the M.2 B Key slot may be damaged.
Figure 58
CON24 is a dedicated Micro SIM card holder for 5G modules. It adopts the form of inserting the card and self-bouncing, without detection pins.
Figure 59
Figure 60
Design Considerations:
(1) In order to ensure stable VDD_3V3_PCIE power output, it is recommended to use WD1304E30-6/TR(U8) for independent power supply.
Figure 61
17 4G module expansion interface
CON19 is an expansion interface for 4G modules, using Mini PCIe slots. The evaluation board expands the USB0 bus to 4 USB HOST buses through the USB HUB chip, and one of them leads to 4G module expansion.
CON18 is a dedicated Micro SIM card holder for 4G modules, which adopts the card self-ejection form and does not have a detection pin.
Figure 62
Figure 63
Design Considerations:
(1) In order to ensure stable VDD_3V3_4G power output, it is recommended to use WD1304E30-6/TR(U93) for independent power supply.
Figure 64
18 WIFI modules
The evaluation board expands the USB0 bus to 4 USB HOST buses through the USB HUB chip, and one of them leads to WIFI module expansion. The model of the on-board WIFI module (U32) is: Bilian BL-R8188EU2, which adopts the stamp hole connection method.
CON20 is an SMA interface, which is used to connect the 2.4G antenna of the external WIFI module.
Figure 65
Figure 66
19 ADC interface
J11 is the ADC interface. It adopts 2x 10pin specification and 2.54mm spacing to lead out 8 analog input channels. The sampling rate is as high as 4MSPS, and the voltage input range is generally 0 ~ 1.8V.
Note: This function is only for AM6442.
Figure 67
Figure 68
Design Considerations:
(1) The ADC input voltage range is 0 ~ 1.8V. When designing the backplane, it is necessary to pay attention to the input signal not exceeding the above required range, otherwise the core board may be damaged.
20 DI/DO interface
J9 is an optocoupler-isolated DI/DO interface, which uses 10pin specifications and 3.81mm pitch green terminals to lead out 4 digital inputs and 4 digital outputs.
The power input range of the VDD and GNDI pins of the DI/DO interface is DC 3~24V. When the switch input signal is 3~24V, it will be identified as high level; when the switch input signal is below 1V, it will be identified as low level. The switching output is a high level signal of 3~24V or a low level signal below 1V.
Figure 69
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Figure 72