Foreword
This article mainly introduces the hardware interface resources and design considerations of the TLIMX8MP-EVM evaluation board of Chuanglong Technology.
Chuanglong Technology TLIMX8MP-EVM is a high-performance industrial evaluation board based on NXP i.MX 8M Plus quad-core ARM Cortex-A53 + single-core ARM Cortex-M7 heterogeneous multi-core processor design. It consists of a core board and an evaluation base board . The ARM Cortex-A53 (64-bit) main processing unit has a main frequency of up to 1.6GHz, and the ARM Cortex-M7 real-time processing unit has a main frequency of up to 800MHz. The processor adopts the latest 14nm technology, built-in 2.3TOPS computing power NPU neural network processing unit, dual-channel independent ISP image processing unit, dual-core GPU graphics accelerator, and supports 1080P60 H.264/H.265 video hardware codec, three-screen different display function. The core board has been verified by professional PCB layout and high and low temperature tests. It is stable and reliable, and can meet various industrial application environments.
The evaluation board is rich in interface resources, leading to 3x USB3.0 HOST, RS232, 2x CAN-FD, 2x RS485, dual Gigabit Ethernet ports (one supports TSN), 100M Ethernet ports and other communication interfaces, onboard WIFI module, supports 4G , 5G module, supports NVMe solid-state hard disk, and leads out audio and video multimedia interfaces such as MIPI LCD, LVDS LCD, HDMI OUT, CAMERA, LINE IN, LINE OUT, MIC IN, etc., which is convenient for users to quickly conduct product solution evaluation and technology pre-research.
The TLIMX8MP-EVM evaluation board uses the NXP i.MX 8M Plus processor, the IO level standard is generally 1.8V and 3.3V, and the pull-up power supply generally does not exceed 3.3V. When the external signal level does not match the IO level, a level conversion chip or signal isolation chip needs to be added in the middle. ESD design needs to be considered for buttons or interfaces. When selecting ESD devices, attention should be paid to whether the junction capacitance is too large, otherwise it may affect signal communication.
Figure 1 TLIMX8MP-EVM hardware resource diagram 1
Figure 2 TLIMX8MP-EVM hardware resource diagram 2
The hardware reference directory is as follows:
(1) "SOM-TLIMX8MP Industrial Core Board Hardware Manual": "\5-Hardware Information\Core Board Information\"SOM-TLIMX8MP Industrial Core Board Hardware Manual"";
(2) TLIMX8MP-EVM evaluation board schematic diagram: "\5-hardware information\evaluation board schematic diagram\TLIMX8MP-EVM evaluation board schematic diagram\";
(3) "TLIMX8MP-EVM Evaluation Board BOM": "\5-Hardware Information\Evaluation Board Schematics\TLIMX8MP-EVM Evaluation Board Schematics\"TLIMX8MP-EVM Evaluation Board BOM"";
(4) TLIMX8MP-EVM Evaluation Board PCB: "\5-Hardware Information\Evaluation Board PCB\TLIMX8MP-EVM Evaluation Board PCB\";
(5) Evaluation board B2B connector package: "\5-hardware information\evaluation board PCB\TLIMX8MP-EVM evaluation board B2B connector package\";
(6) STP file of SOM-TLIMX8MP core board: "\5-hardware information\core board information\SOM-TLIMX8MP core board STP file\";
(7) SOM-TLIMX8MP core board DXF file: "\5-hardware information\core board information\SOM-TLIMX8MP core board DXF file\";
(8) Evaluation board component data sheet: "\6-Development Reference Materials\Data Sheet\".
1 SOM-TLIMX8MP core board
The SOM-TLIMX8MP core board is equipped with CPU, ROM, RAM, crystal oscillator, power supply, LED and other hardware resources, and leads out IO through industrial-grade B2B connectors. For detailed content such as core board hardware resources, pin descriptions, electrical characteristics, mechanical dimensions, and backplane design considerations, please refer to the "SOM-TLIMX8MP Industrial Core Board Hardware Manual".
Figure 3 Core board hardware block diagram
Figure 4 Front view of the core board
Figure 5 Physical picture of the back of the core board
2 B2B connectors
The evaluation board uses 4 industrial-grade B2B connectors from Linkwork, with a total of 320 pins, a pitch of 0.5mm, and a combined height of 4.0mm. Two 80pin male B2B connectors (CON0B, CON0D), model NLWBP05-80C-1.0H, height 1.0mm; two 80pin female B2B connectors (CON0A, CON0C), model NLWBS05-80C-3.0H, height 3.0mm.
Figure 6 The physical picture of the B2B connector on the evaluation board
3 power connector
The evaluation base board is powered by a 12V DC power supply, and CON1 and CON2 are power input connectors.
CON1 is a 3pin green terminal with a pitch of 3.81mm. CON2 is a DC-005 power interface, which can be adapted to a power plug with an outer diameter of 5.5mm and an inner diameter of 2.1mm. The power input terminal has circuit protection functions such as over-current protection, over-voltage protection, anti-reverse insertion and rapid power-off. SW1 is a power toggle switch, please select it according to the ON/OFF silk screen nearby when using it.
Figure 7 Physical diagram of the power interface
Figure 8 Input stage power supply protection circuit
VDD_12V0_MAIN is converted to supply power for the core board and the peripherals of the evaluation board through multiple power supply chips. The recommended power-on sequence for the evaluation board: 12V DC power supply (VDD_12V0_MAIN) -> core board power supply (VDD_5V0_SOM) -> core board configuration base board auxiliary power supply (VDD_3V3_SOM) -> base board peripheral power supply -> system reset (J29/POR_B/PU/ 1V8), the recommended power-on sequence design is shown in the figure below.
Figure 9 Recommended power-on sequence for the evaluation board
3.1 Core board power supply
VDD_12V0_MAIN outputs VDD_5V0_SOM for the core board through EC2232E (DC-DC power step-down chip) of Ecranic, and the maximum current supply capacity is 3A.
The power enable is provided by the input voltage divider to realize the timing control of power-on. In order to protect the core board and facilitate the measurement of voltage and current, the power path has been connected to the magnetic bead FB1 in series, and the default maximum current of the actual circuit is 2A.
Figure 10 Core board power supply design
The core board provides VDD_3V3_SOM power output, which is used to control the power-on sequence of each power supply on the evaluation board.
3.2 Evaluating Backplane Peripheral Power
VDD_12V0_MAIN outputs VDD_5V0_MAIN, VDD_3V3_MAIN, VDD_3V3_PCIe_5G, and VDD_1V8_MAIN through 4-way Ecranic EC2232E (DC-DC power step-down chip) for the evaluation of peripherals on the backplane, and the maximum current supply capacity is 3A. The 4-way power supply is provided by VDD_3V3_SOM to realize the timing control of power-on of the peripheral circuits on the evaluation board after the core board.
Note: VDD_3V3_PCIe_5G power enable is also controlled by AE14/GPIO3_IO24/PCIE_POWER_CTL/1V8 signal.
Figure 11 VDD_5V0_MAIN power supply design
Figure 12 VDD_3V3_MAIN power supply design
Figure 13 VDD_3V3_PCIe_5G power supply design
Figure 14 VDD_1V8_MAIN power supply design
3.3 Isolated power supply
VDD_5V0_MAIN outputs a 5V DC isolated power supply VDD_5V0_ISO through the B0505S-1WR3L isolated power module of MORNSUN, which is used to evaluate the power supply of the backplane isolation circuit. The maximum current supply capacity is 200mA, and it can provide 3000V DC DC isolation capacity.
Figure 15 VDD_5V0_ISO power supply design
Design Considerations:
(1) When designing the backplane, if some or all functions of the protection circuit of the power input stage are not required, it can be cut appropriately.
(2) The design of the backplane power supply can be increased or decreased according to the actual circuit design. It is recommended to refer to our company's power-on sequence for enabling control of the backplane power supply.
(3) VDD_5V0_SOM does not reserve a large energy storage capacitor for the total power input inside the core board. When designing the baseboard, please place an energy storage capacitor with a total capacitance of about 50uF near the pad of the B2B connector.
(4) In order to make VDD_5V0_MAIN, VDD_3V3_MAIN, VDD_3V3_PCIe_5G and VDD_1V8_MAIN meet the system power-on and power-off timing requirements, it is necessary to use the core board output VDD_3V3_SOM to control the power enable of VDD_5V0_MAIN, VDD_3V3_MAIN, VDD_3V3_PCIe_5G and VDD_1V8_MAIN , so that the evaluation board VDD_5V0_MAIN, VDD_3V3_MAIN, VDD_3V3_PCIe_5G Power up the VDD_1V8_MAIN power supply after VDD_3V3_SOM and before the J29/POR_B/PU/1V8 reset signal. For details, see the recommended power-on sequence for the evaluation board.
4 LED
The evaluation base board has 4 LEDs on board. LED0 is the power indicator light, the color is red, and it is on by default when it is powered on; LED1 is a user-programmable indicator light, controlled by GPIO, the color is green, and the default high level is on; LED2 is the 4G module status indicator light, the color is yellow ; LED3 is the NVMe SSD/5G module status indicator, the color is yellow.
Figure 16 LED0~LED3 physical map
Figure 17 Evaluation board power indicator
Figure 18 User Programmable Indicators
Figure 19 4G module status indicator
Figure 20 NVMe SSD/5G module status indicator
5 BOOT SET Start mode selection DIP switch
SW2 is a 4bit start mode selection dial switch. The common startup modes are as follows, please confirm the startup method according to the silkscreen on the evaluation board and select the dial position.
(1) Micro SD mode: 1100(1~4).
(2) eMMC mode: 0100(1~4).
(3) USB Serial Download mode: 1000(1~4).
Remarks: When the configuration is selected as USB Serial Download mode, the evaluation board supports curing the system from USB3.0 DRD (USB1).
Figure 21 The physical picture of the start mode selection DIP switch
Figure 22 BOOT SET configuration circuit selection
Design Considerations:
(1) The BOOT_MODE[0:3] pin is used to select the boot mode through the BOOT SET boot selection DIP switch or pull-up and pull-down resistors on the evaluation board. Please refer to the evaluation board BOOT SET circuit to design the boot configuration circuit, especially the resistance value of the pull-up and pull-down resistors must refer to the resistance parameters used in the evaluation board for selection.
(2) Please use the VDD_1V8_SOM power output from the core board for the BOOT_MODE[0:3] pins. VDD_1V8_SOM is a power supply dedicated to BOOT SET configuration and QSPI NOR FLASH. The current supply capacity is 100mA. Do not use it for other loads.
(3) Before the POR_B signal is set high, please ensure that the level status of the BOOT_MODE[0:3] signal is not changed.
6 KEY
The evaluation board includes a system cold reset button COLD RESET (KEY1), a CPU switch button CPU ON/OFF (KEY2), and a user input button USER (KEY3).
Figure 23 KEY physical map
Figure 24 System reset, CPU switch button
Figure 25 User input button
Design Considerations:
(1) PMIC_KEY_RSTn is the power-on reset input pin of the PMIC, which has been pulled up to 1.8V inside the PMIC. Please leave it floating when not in use.
(2) G22/ONOFF is the on/off control pin of the CPU. Press and hold for more than 5s to shut down the CPU, and press it for about 1s to switch the CPU to power on. A 100K pull-up resistor has been designed inside the core board, please leave it floating when not in use.
7 serial port
The evaluation board has UART, RS232 and RS485 serial ports onboard, CON5 is the USB TO UART2 debugging serial port, CON7 is the UART1 serial port, CON9 is the UART3 serial port, CON8 is the RS232 UART4 serial port, and CON28 contains the RS485 UART1 and RS485 UART3 serial ports.
7.1 USB TO UART2 serial port
The evaluation board converts UART2 into a Type-C connector (CON5) through the CH340T chip of Qinheng Microelectronics (WCH) and leads it out as a system debugging serial port. The CH340T uses the 5V power supply UART_VBUS from the Type-C line for external power supply.
Figure 26 USB TO UART2 serial port physical map
Figure 27 USB TO UART2 serial port circuit design
Design Considerations:
(1) When designing the base board, it is recommended to use the RS0102YVS8 (U12) level conversion isolation scheme to prevent the RX terminal of the debugging serial port from being charged in advance before the base board is powered on, and inject current into the core board pins, causing the system to fail to start.
(2) The CPU pins UART2_TXD and UART2_RXD are both 3.3V in level, please do not use a debugging tool with a 5V level interface to connect them directly, otherwise the CPU may be damaged.
(3) Note that the USB signal needs to do 90ohm differential impedance matching.
(4) The ESD device should be placed close to the Type-C interface of the connector, and the wiring should be connected to the CH340T after passing through the ESD.
7.2 UART1/UART3 serial port
The evaluation board adopts 4pin specification, 2.54mm pitch white terminals (CON7, CON9), which directly leads to UART1, UART3 serial ports.
Figure 28 UART1, UART3 serial port physical map
Figure 29 UART1, UART3 serial port circuit design
Design Considerations:
(1) UART1 interface and RS485 UART1 interface share the same group of UART1 bus, UART3 interface and RS485 UART3 interface share the same group of UART3 bus, do not use the same group of UART bus interfaces at the same time.
7.3 RS232 UART4 serial port
The evaluation board adopts the single-power dual-channel RS232 transceiver SIT3232EEUE solution of SIT Electronics (SIT), which leads to one RS232 serial port through UART4 and uses the DB9 connector (CON8).
SIT3232EEUE conforms to TIA/EIA-232 standard, and the maximum communication rate can reach 120Kbps.
Figure 30 RS232 UART4 serial port physical map
Figure 31 RS232 UART4 serial port circuit design
7.4 RS485 UART1/RS485 UART3 serial port
The evaluation board adopts the isolated half-duplex RS485 transceiver CA-IS3082WX solution of CHIPANALOG, which converts UART1 and UART3 into two RS485 serial ports. The 2-way RS485 serial port and the CAN interface share a 10pin specification and a 3.81mm pitch green terminal (CON28).
CA-IS3082WX complies with TIA/EIA-485-A standard, supports 5kVrms insulation withstand voltage, bus common mode working range: -7V~+12V, and provides up to 0.5Mbps communication rate.
Figure 32 RS485 UART1/RS485 UART3 serial port physical map
Figure 33 RS485 UART1/RS485 UART3 serial port circuit design
Figure 34
Design Considerations:
(1) CA-IS3082WX is an isolated RS485 transceiver; among them, Vcc1 (pin1) and GND1 (pin7/8) are the power supply for the logic side port, and Vcc2 (pin16) and GND2 (pin9/10) are the power supply for the bus side port. Vcc1 should be electrically isolated from Vcc2, GND1 and GND2 should not share the same ground, and attention must be paid to isolation design on device layout and routing, otherwise the design purpose of the isolated interface cannot be achieved. It is recommended that the reference evaluation board use an isolated power supply to power Vcc2.
(2) Vcc1 provides a wide IO power supply range of 2.375V~5.5V, and the bus-side power supply Vcc2 provides a RS485 bus power supply range of 3.0V~5.5V.
(3) The pins A/B (pin12/13) of the transceiver are connected to the traces between the green terminal connectors, which need to be traced according to differential signals.
(4) UART1 interface and RS485 UART1 interface share the same group of UART1 bus, UART3 interface and RS485 UART3 interface share the same group of UART3 bus, do not use the same group of UART bus interfaces at the same time.
8 CAN1/CAN2 interface
The evaluation board leads CAN1 and CAN2 interfaces through two isolated transceivers NSI1042-DSWVR from NOVOSENSE, and shares the green terminal (CON28) of 10pin specification and 3.81mm spacing with the RS485 serial port.
NSI1042-DSWVR conforms to the ISO11898-2 standard, and the power supply voltage is 3.3V (VDD_3V3_MAIN). Support 5kVrms insulation withstand voltage, bus common mode working range: -30V~+30V, the highest communication rate is 5Mbps.
Figure 35 CAN1/CAN2 interface physical map
Figure 36 CAN1/CAN2 circuit design
Figure 37 CAN circuit design
Design Considerations:
(1) NSI1042-DSWVR is an isolated CAN transceiver. Among them, VCC1 (pin1) and GND1 (pin4) supply power to the ports on the logic side, and VCC2 (pin8) and GND2 (pin5) supply power to the ports on the bus side. VCC1 should be electrically isolated from VCC2, GND1 and GND2 should not share the same ground, and attention should be paid to isolation design on device layout and routing, otherwise the design purpose of the isolated interface cannot be achieved. It is recommended to refer to our company to use an isolated power supply to supply power to VCC2.
(2) VCC1 provides a wide IO power supply range of 2.5V~5.5V, and VCC2 provides a CAN bus side power supply range of 4.5V~5.5V.
(3) The wiring between CANH (pin7) and CANL (pin6) and the green terminal connector needs to be wired as a differential signal.
(4) CANH (pin7) and CANL (pin6) should be connected in parallel with a terminal matching resistor (R98, R104) with an accuracy of 1%. The size of the terminal matching resistance is determined by the characteristic impedance of the transmission cable, generally 120ohm.
(5) It is recommended to refer to the ESD device model PESD2CANFD24V-K used in the evaluation board, or use other ESD devices with a capacitance value less than or equal to 15pF, and the common-mode voltage value must support at least +/-12V.
9 Micro SD interface
The evaluation baseboard leads to a Micro SD interface through the uSDHC2 bus, using 4bit data line mode. The specification used is an external soldering Micro SD connector (CON4) with a pressing piece on the shell.
Figure 38 Micro SD interface physical map
Figure 39 Micro SD interface circuit design
Design Considerations:
(1) When designing the backplane, it is necessary to connect the SHIELD[1:4] pins of the Micro SD socket shell to the digital ground.
(2) It is recommended to use the output power VDD_3V3_SD of the core board to power the Micro SD (CON4). It is not recommended to use VDD_3V3_MAIN for power supply, otherwise the system may fail to read the Micro SD card device correctly due to the power supply delay of this power supply.
10 External RTC socket
The evaluation board adopts the serial real-time clock chip DS1307ZM/TR of Arima Semiconductor (HGSEMi), which expands the function of the external RTC and uses the I2C1 bus for communication. CON3 is an RTC button battery holder, which can be used with button batteries ML2032 (3V rechargeable) and CR2032 (3V not rechargeable). When using a rechargeable battery, the jumper cap can be inserted into the J1 interface to realize charging. When using a non-rechargeable battery, please do not insert the jumper cap into the J1 interface.
Figure 37 Physical diagram of external RTC circuit
Figure 40 External RTC circuit design
Design Considerations:
(1) U8 can choose DS1307ZM/TR, DS1340Z-33+ and ISL1208IB8Z-TK. If you choose to paste DS1340Z-33+ and ISL1208IB8Z-TK, you need to paste FB4 solidly and FB3 empty, and use VDD_3V3_MAIN for power supply.
(2) I2C1 has been connected to the PMIC power management chip of the core board. I2C1 does not add a pull-up resistor on the core board. Please be sure to pull the 4.7K resistor to 3.3V on the bottom board.
11 External Watchdog interface
The evaluation board adopts the external hardware watchdog chip MAX6369KA+T from Maxim Integrated to expand the external Watchdog function. J3 is the interface for configuring the Watchdog function. It adopts a 2.54mm pitch and a 3-pin pin header. The Watchdog function can be enabled by configuring a jumper cap. The watchdog timeout period can be configured through U25/GPIO2_IO9/WD_SET0/3V3 on the software.
Figure 41 Physical diagram of external Watchdog circuit
Figure 42 External Watchdog circuit design
Figure 43
Figure 44
12 FAN power supply interface
J2 is the radiator fan power interface (FAN), which adopts 3pin header terminal mode, 12V power supply, and the spacing is 2.54mm.
Figure 45 Physical diagram of FAN power supply interface
Figure 46 FAN power supply interface circuit design
13 LINE IN/MIC IN/LINE OUT接口
The evaluation board adopts Texas Instruments (TI) TLV320AIC3106IRGZ audio chip, leading out LINE IN (CON11), MIC IN (CON25) and LINE OUT (CON10) a total of 3 audio interfaces, all using 3.5mm audio jacks.
The CPU communicates with the TLV320AIC3106IRGZ through the SAI3 bus, and uses I2C1 for configuration, and the address is 0x18.
Figure 47 Physical diagram of LINE IN/MIC IN/LINE OUT interface
Figure 48 LINE IN/MIC IN/LINE OUT interface circuit design
Design Considerations:
(1) If the external clock source is not used, the R364 resistor can be pasted empty, and the R365 resistor can be pasted solidly.
14 MIPI LCD interface
J5 is the MIPI LCD display interface, using a 40pin FFC connector with a pitch of 0.5mm.
J6 is the capacitive touch interface CAP TS of MIPI LCD, which uses a 6pin FFC connector with a pitch of 0.5mm. The evaluation board communicates with its connection using the I2C3 bus.
Figure 49 MIPI LCD interface physical map
Figure 50 MIPI LCD interface circuit design
Design Considerations:
(1) To ensure that the nINT pin of CAP TS (J6) is functional, please add a 100K pull-up resistor.
(2) The nINT pin of CAP TS (J6) needs to use a GPIO pin that supports interrupt function;
(3) Since HDMI2 OUT and MIPI LCD interface share the MIPI_DSI1 bus, HDMI2 OUT and MIPI LCD interface cannot be used at the same time.
(4) The touch screen generally has two optional I2C addresses. When RESET (RST) is powered on, it will read the high and low levels of the INT (nINT) pin signal to select the I2C address of the touch screen.
Figure 51 Explanation diagram of touch screen power-on sequence and address selection
15 CAMERA1/CAMERA2 interface
The evaluation board leads to the camera interface of CAMERA1 (J8) and CAMERA2 (J9) respectively through the MIPI_CSI1 and MIPI_CSI2 buses, both of which use 30pin FFC connectors with a spacing of 0.5mm.
The evaluation board configures CAMERA1 and CAMERA2 using I2C1 and I2C2 buses respectively.
Figure 52 Physical diagram of CAMERA1/CAMERA2 interface
Figure 53 CAMERA1/CAMERA2 interface circuit design
Design Considerations:
(1) Since the signal level of the CAMERA1/CAMERA2 camera interface is 1.8V, but the I2C1, I2C2, CCM_CLKO1 and CCM_CLKO2 signal levels output by the core board are 3.3V, it is necessary to convert the level to 1.8V before connecting to CAMERA1/CAMERA2 interface is used.
16 HDMI OUT interface
16.1 HDMI1 OUT interface
The evaluation base board directly leads to the HDMI1 OUT (CON21) video output interface through the HDMI bus, using a standard 19pin HDMI connector. Support HDMI 2.0 standard, support 2160P ultra-high-definition video output.
Figure 54 Physical picture of HDMI1 OUT interface
Figure 55 HDMI1 OUT interface circuit design
Design Considerations:
(1) The HDMI interface HPLG signal needs to input a 3.3V signal to the core board through the voltage dividing resistor (R294, R297), and the HPLG signal can be connected to a 3.3V or 5V level IO. When an external device is connected, this signal will be pulled high.
(2) Do not use the VDD_5V0_HDMI1 power output from the HDMI interface to power other loads.
(3) The IO level of AC22/HDMI_DDC_SCL/3V3 and AF22/HDMI_DDC_SDA/3V3 is 3.3V, which needs to be converted to 5V level and then led to the HDMI interface. In order to prevent power feeding through the HDMI interface when the core board is powered off, it is necessary to refer to the circuit design of the evaluation board to add D32 and D33 devices.
16.2 HDMI2 OUT interface
The evaluation board adopts Lontium's LT8912B chip solution, expands the HDMI2 OUT interface through the MIPI_DSI1 bus, and uses a standard 19pin HDMI connector. Support HDMI1.4 standard, support 1080P high-definition video output.
Figure 56 Physical picture of HDMI2 OUT interface
Figure 57 HDMI2 OUT interface circuit design
Figure 58 HDMI2 OUT interface circuit design
Design Considerations:
(1) Since the HDMI2 OUT interface is extended by MIPI_DSI1, please do not use HDMI2 OUT and MIPI LCD interface at the same time.
(2) Do not use the VDD_5V0_HDMI2 power output from the HDMI interface to power other loads.
(3) In order to prevent power feeding through the HDMI interface when the core board is powered off, it is necessary to add a D34 device by referring to the evaluation board circuit.
17 LVDS LCD interface
CON23 is a dual-channel 8bit LVDS LCD interface, using 30pin double-row pins with a pitch of 2.0mm, including LVDS signal and power supply. CON24 is the BACK LIGHT backlight control interface, using a 6pin white terminal block with a pitch of 2.0mm. J7 is the RES TS resistive touch screen interface, using 4pin pin headers with a pitch of 2.54mm.
Figure 59 LVDS LCD interface physical map
Figure 60 LVDS LCD interface circuit design
Figure 61 RES TS resistive touch screen interface circuit design
Design Considerations:
(1) The terminal matching resistor 100R of the LVDS differential pair should be placed close to the CON23 interface.
18 USB ports
The evaluation board leads to 4 USB ports. CON12, CON13, and CON14 are USB3.0 HOST interfaces, using side-plug Type-A connectors; CON6 is a USB3.0 DRD interface, using Type-C connectors.
18.1 USB3.0 HOST interface
The evaluation board adopts the 4-port USB3.0 HUB controller CYUSB3314-88LTXIT of Cypress (CYPRESS), which expands the USB2 bus to 4 USB3.0 HOST, and leads 3 of them to USB3.0 HOST1, USB3. 0 HOST2, USB3.0 HOST3 interface, expand the other 1 USB3.0 HOST (USB2_HUB1) bus to 4 USB2.0 HOST buses through the USB2.0 HUB chip (CH334H).
The CYUSB3314-88LTXIT chip conforms to the USB3.0 protocol specification and supports Super Speed (SS), High Speed (HS), Full Speed (FS) and Low Speed (LS) modes.
Figure 62 USB3.0 HOST interface physical map
Figure 63 USB3.0 HOST interface circuit design
Figure 64 USB3.0 HOST interface circuit design
Figure 65 USB3.0 HOST interface circuit design
Figure 66 USB3.0 HOST interface circuit design
Design Considerations:
(1) The AC coupling capacitors (C128, C129) of US_RXM and US_RXP pins in CYUSB3314-88LTXIT should be placed close to the chip (U33), and the AC coupling capacitors (C372 and C371) of US_TXM and US_TXP should be placed close to the core board B2B connector.
18.2 USB3.0 DRD interface
CON6 is a USB3.0 DRD interface, using a 24pin Type-C female socket, which is led out from the core board through the USB1 bus.
The evaluation board uses the Type-C control chip WUSB3801Q-12/TR of WILLSEMI to realize the detection function of the communication role.
Since the USB3.0 differential pair signal rate is as high as 5Gbps, it cannot be directly bifurcated and connected to the front and back of the Type-C interface in the USB2.0 way. It is recommended to use the USB switch chip CH482D of Qinheng Microelectronics (WCH) to realize the positive and negative connection function. One-two switching for differential signals.
Figure 67 USB3.0 DRD interface physical map
Figure 68 USB3.0 DRD interface circuit design
Design Considerations:
(2) The AC coupling capacitors (C374, C373, C377, C376) of TX1+, TX1-, TX2+, TX2- in CH482D should be placed close to the chip (U27).
19 Ethernet interface
The evaluation board contains 2 ETH RGMII Gigabit Ethernet ports and 1 ETH USB 100M Ethernet port.
The CPU integrates 2 Gigabit Ethernet controllers and supports 2 native RGMII Gigabit Ethernet ports, one of which ENET_QOS supports the TSN industrial protocol.
19.1 ETH1/ETH2 Gigabit Ethernet port
The evaluation board adopts Motorcomm's YT8521SH-CA integrated Ethernet transceiver solution to provide 2-way 10/100/1000Mbps adaptive Ethernet, using double-layer Gigabit RJ45 connectors, and the RJ45 connectors have built-in isolation transformer. The lower layer is the ETH1 Gigabit Ethernet port, and the upper layer is the ETH2 Gigabit Ethernet port.
The 2 Gigabit Ethernet ports use independent RGMII bus and MDIO bus to realize PHY communication and configuration. Among them, ETH1 is controlled by the ENET1_RGMII bus, and ETH2 is controlled by the ENET_QOS_RGMII bus.
YT8521SH-CA complies with 10BASE-Te, 100BASE-TX and 1000BASE-T IEEE802.3 standards, and provides functions such as cross detection, automatic correction, polarity correction and adaptive equalization.
Figure 69 ETH1/ETH2 Gigabit Ethernet port physical map
Figure 70 ETH1 interface circuit design
Figure 71 ETH2 interface circuit design
Design Considerations:
(1) The PHYs of ETH1 and ETH2 use 1.8V IO level. The corresponding RGMII bus level selection is configured through CFG_LDO[1:0], and the power supply pin of the corresponding circuit is DVDD_RGMII of the YT8521SH-CA chip.
(2) XTAL_I, XTAL_O pins are connected to 25MHz passive crystal oscillator. If you need to use a 25MHz active crystal oscillator, you can access it from the XTAL_I pin and leave the XTAL_O pin floating.
(3) The YT8521SH-CA scheme adopted by the evaluation board uses the internally generated 1.2V voltage (VDD_1V2_ETH1, VDD_1V2_ETH2) for the core logic power supply, and does not need to provide an additional 1.2V voltage. Do not use VDD_1V2_ETH1 and VDD_1V2_ETH2 to supply power to other loads.
(4) The YT8521SH-CA chip is required to keep the power supply stable for 100ms before pulling the reset signal high; it is recommended to use IO to control the reset of the PHY chip.
(5) PCB layout instructions:
a) ESD devices should be placed close to the RJ45 connector.
b) The MDIx_P/N_D signal should be routed as a 100ohm differential signal, and the clock signal provided by the crystal oscillator is recommended to be grounded.
c) The two sets of signals for sending and receiving in the RGMII bus should be treated with equal lengths of ±50mil respectively. Please pay attention to obtain the wiring length of the corresponding signals in the core board provided in the core board hardware manual.
19.2 ETH3 (USB2) 100M network port
The evaluation base board adopts the SR9900AI integrated Ethernet control circuit solution of Hexin Runde Technology Co., Ltd., and expands 1 channel of 10/100Mbps adaptive Ethernet through the USB2_HUB1_1 bus, using the 100M RJ45 socket (CON16) with a built-in isolation transformer.
SR9900AI complies with IEEE802.3 10Base-T/100Base-TX and IEEE802.3 100Base-FX standards, and provides polarity and phase offset correction, network cable cross detection and automatic correction functions.
Remarks: The evaluation board uses a USB2.0 HUB chip (CH334H) to expand the USB2_HUB1 bus to 4 USB2.0 HOST buses, and expand one of the USB2_HUB1_1 buses to the ETH3 (USB2) 100M Ethernet port.
Figure 72 ETH3 (USB2) 100M network port physical map
Figure 73 ETH3 (USB2) 100M network port circuit design
Design Considerations:
(1) The PESDALC10N5VU near the RJ45 connector is an ESD device in a 10-pin package. Please note that the two side-by-side pins (such as IN1 and NC4, IN2 and NC3) are not connected inside the ESD device. In actual design, the corresponding pins should be Direct external short-circuit processing (as shown in the figure below), that is, the network names of the corresponding pins must be consistent, which is convenient for PCB wiring.
Figure 74 ESD circuit design
20 4G module interface
CON17 is a 4G module expansion interface, using Mini PCIe slot. Compatible with Quectel EM05CEFC-128-SGAS 4G module. The evaluation board expands the USB2_HUB1 bus to 4 USB2.0 HOST buses through the USB2.0 HUB chip (CH334H), and expands one of the USB2_HUB1_2 buses to a 4G module.
Figure 75 4G module interface physical map
CON19 is the Micro SIM card holder shared by the 4G module and the 5G module. It adopts the card self-ejection form and does not have a detection pin. When using it, the corresponding Micro SIM card must be inserted correctly.
Figure 76 Physical picture of 4G/5G Micro SIM card holder
Figure 77 4G module interface circuit design
Design Considerations:
(1) In order to ensure the stable power supply of the 4G module, its 3.3V power supply must be independently powered by MIC29302S/TR, providing at least 2A current output. If you need to replace other power supplies, it is recommended to use an LDO. For details, please refer to the requirements in the 4G module data sheet.
(2) If you need to control the power supply of the 4G module, you can paste the R219 and R221 resistors, and control the power enable status of the 4G module through GPIO.
21 M.2 PCIe NVMe/5G ports
CON20 is an expansion interface for NVMe SSD/5G module. It adopts M.2 B Key slot, expands through PCIe 3.0 bus, supports PCIe Gen3 standard, and has a maximum communication rate of 8Gbps. It is used as PCIe RC (Root Complex) by default. Compatible with Quectel RM500Q-GL 5G module and M.2 B Key interface type NVMe solid state drive.
The evaluation board expands the (CH334H) USB2_HUB1 bus to 4 USB2.0 HOST buses through the USB2.0 HUB chip, and expands one of the USB2_HUB1_4 buses to 5G modules.
The evaluation board uses the clock chip PI6C557-03BLEX from Diodes, which outputs 2 channels of HCSL level differential clocks, of which 1 channel is provided to the M.2 PCIe NVMe/5G interface (CON20), and the other 1 channel is provided to It is used inside the core board.
Figure 78 M.2 PCIe NVMe/5G interface physical map
Figure 79 M.2 PCIe NVMe/5G interface circuit design
Design Considerations:
(1) In order to ensure stable VDD_3V3_PCIe_5G power output, it is recommended to use EC2232E(U6) for independent power supply.
(2) The 5G module and the 4G module share the 4G/5G Micro SIM card holder (CON19), which adopts the card self-ejection form without detection pins. When using it, the corresponding Micro SIM card must be inserted correctly.
22 WIFI modules
U51 is the onboard WIFI module, the model is BL-R8188EU2 of Bilian Company, and it adopts the stamp hole connection method. The evaluation board expands the USB2_HUB1 bus to 4 USB2.0 HOST buses through the USB2.0 HUB chip (CH334H), and expands 1 USB2_HUB1_3 bus to the WIFI module.
Figure 80 WIFI module physical map
CON18 is the WIFI SMA interface, which is used to connect the 2.4G antenna of the external WIFI module.
Figure 81 WIFI SMA interface physical map
Figure 82 WIFI module circuit design
23 DI/DO interface
CON29 is an optocoupler-isolated DI/DO interface. It adopts 10pin specification and 3.81mm spacing green terminal method, leading to 4 digital inputs and 4 digital outputs.
The power input range of the VDD and GNDI pins of the DI/DO interface is DC 3~24V. When the switch input signal is 3~24V, it will be identified as high level; when the switch input signal is below 1V, it will be identified as low level. The switching output is a high level signal of 3~24V or a low level signal below 1V.
Figure 83 Physical diagram of DI/DO interface
Figure 84 DI/DO interface circuit design
24 EXPORT expansion interface
The evaluation board provides 1-way expansion IO signal interface J12. It adopts 2x 20pin specification pin arrangement with a pitch of 2.54mm to lead out expansion signals such as POR_B, I2C, SPI, CLK, EARC, and GPIO 3V3/1V8.
Remarks: The IO signal level from the EXPORT interface is not consistent, please confirm the level standard of the selected signal when using it.
Figure 85 Physical diagram of EXPORT interface
Figure 86 EXPORT interface circuit design
Design Considerations:
(1) B6/GPIO1_IO02/PMIC_WDOG_B/PU/3V3, D6/GPIO1_IO03/PMIC_nINT/3V3 and AD28/GPIO2_IO19/PMIC_SW_EN/PU/1V8 have been connected to the PMIC (power management chip) inside the core board, do not connect it when designing the bottom board to other functions.