Principles of computer composition: 5. Input and output systems

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5.1 Overview of I/O system

5.1.1 Overview of the development of input and output systems

early stage

There were fewer types of I/O devices in the early days, and information exchanged between I/O devices and main memory must pass through the CPU:

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Each I/O device must be equipped with a set of independent logic circuits connected to the CPU, and the lines are very scattered and complicated .
The input and output process is interspersed in the process of CPU executing the program, and the work efficiency is low .
The logic control circuit of each I/O device and the controller of the CPU form an inseparable whole closely, and the scalability is low .

Interface block and DMA stage

At this stage, the I/O device is connected to the host through the interface module, and the computer system adopts the bus structure:

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The data not only plays a buffer role through the interface, but also completes the string-to-parallel conversion.
The interface can meet the requirements of interrupt request processing, so that the I/O device and the CPU can work in parallel, which greatly improves the working efficiency of the CPU.
Interface technology can also enable multiple I/O devices to occupy the bus in time-sharing, so that multiple I/O devices can also work in parallel with each other, which is conducive to improving the work efficiency of the whole machine.

In order to further improve the working efficiency of the CPU, a direct memory access (Direct Memory Access, DMA) technology has emerged:

There is a direct data path between the I/O device and main memory;
The I/O device can directly exchange information with the main memory, so that the CPU can continue to complete its own work when the I/O device exchanges information with the main memory, so the resource utilization rate has been further improved.

stage with channel structure

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A channel is a component responsible for managing I/O devices and exchanging information between main memory and I/O devices.
The channel has a dedicated channel instruction, which can independently execute the input and output program written by the channel instruction, and is a dedicated processor subordinate to the CPU.
When the I/O devices that rely on channel management exchange information with the host, the CPU does not directly participate in the management, so the resource utilization of the CPU is improved.

Stages with I/O handlers

The input and output system developed to the fourth stage, and the I/O processor appeared:

The I/O processor is also called the peripheral processor (Peripheral Processor);
It basically works independently of the host, and can not only complete the I/O control to be completed by the I/O channel, but also complete code system conversion, format processing, data block error detection, error correction and other operations.
The I/O system with the I/O processor has a higher parallelism with the CPU, which means that the I/O system has greater independence from the host.

5.1.2 Composition of input and output system

Input and output system:

I/O software
I/O hardware

I/O software

The main tasks of the input and output system software are as follows:

Enter the program (or data) compiled by the user into the host.
Send the result of the operation to the user.
Realize the coordination of the input and output system and the host computer.

composition:

I/O instruction: A type of machine instruction, whose device code is equivalent to the address of the device, and is used to select a certain device to exchange information with the host.
Channel command: also known as channel control word (Channel Control Word, CCW), is the command of the channel itself, used to perform I/O operations, such as reading, writing, tape transport and disk seek.

I/O hardware

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The hardware composition of the input and output system is various. In the I/O system with interface, it generally includes:

interface module
I/O device two

As shown in FIG:

I/O system with channels;
One channel can be connected to more than one device controller, and one device controller can control several devices of the same type.

5.1.3 Contact method between I/O device and host

When the I/O device exchanges information with the host, there are 5 control methods:

Program query mode: The program query mode is that the CPU continuously inquires whether the I/O device is ready through the program, thereby controlling the I/O device to exchange information with the host.
Program interrupt mode: When the I/O device is ready and sends an interrupt request to the CPU, it will respond.
Direct memory access mode (DMA): There is a data path between the main memory and the I/O device. When the main memory and the I/O device exchange information, there is no need to call the interrupt service program.
I/O channel mode;
I/O processor mode.

5.2 I/O equipment

5.2.1 Overview of I/O Devices

I/O devices can be roughly divided into three categories:

Human-computer interaction equipment: A device that realizes the exchange of information between the operator and the computer.
Storage device for computer information: System software and useful information of various computers have a huge amount of information and need to be stored and kept.
Machine-machine communication equipment: A device that realizes communication tasks between a computer and other computers or with other systems.

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5.2.2 Input devices

The input device completes functions such as inputting programs, data and operating commands:

Keyboard: Input various information, such as Chinese characters, foreign languages, numbers, etc., to the host according to certain specifications through each key on the keyboard.
Mouse: A handheld positioning device, because it is connected to the interface with a long wire, and its shape is a bit like a mouse, so it is named mouse.
Touch screen: It is a positioning device that responds to the contact or proximity of objects. According to different principles, touch screens can be roughly divided into five categories: resistive, capacitive, surface ultrasonic, scanning infrared and pressure sensitive.
Other input devices:
- Light Pen: Similar in shape to a pen, the head is equipped with a lens system that can converge incoming light into a light spot. The rear end of the light pen is connected to the computer input circuit with a wire.
- Brush and graphics tablet: The brush (Stylus) is also in the shape of a pen, but it must be used with a graphics tablet (Tablet).
- Image input device: The most direct image input device is a camera (Camera), which can be digitally quantized and stored as a digital image on a magnetic tape or disk.

5.2.3 Output devices

display screen

Character display:
- Display memory (refresh memory) VRAM: The display memory stores the ASCII codes of the characters to be displayed, and its capacity is related to the number of characters that can be displayed on the display.
- Character generator: convert each ASCII character code into a group of 5×7 or 7×9 dot matrix information.
- CRT controller: It can receive data and control signals from the CPU, and give the address to access the display memory and the raster address to access the character generator, and also give the horizontal synchronization and vertical synchronization signals required by the CRT.
Graphics display: A graphics display is a display device that combines points, lines (straight lines and curves), and surfaces (planes and curved surfaces) to form flat or three-dimensional graphics;
Image display: The graphics displayed by the graphic display are points, lines, planes, shadows, etc. formed by the computer using certain algorithms, which come from the subjective world, so they are also called subjective images or computer images.
Display standards for the IBM PC series of microcomputers:
- MDA (Monochrome Display Adapter) standard: MDA is a monochrome character display standard. It uses a 9×14 dot matrix character window to display 80 columns and 25 rows of characters on the full screen, and the corresponding resolution is 720×350 pixels. MDA is not compatible with graphics displays.
- CGA (Color Graphics Adapter) standard: CGA is a color graphic/character display standard, compatible with both character and graphic display methods. In the character mode, the character window is 8×8 dot matrix, so the character quality is not as good as MDA, but the background color of the character can be selected.
- EGA (Enhanced Graphics Adapter) standard: EGA standard combines the advantages of MDA and CGA two display standards, and has been enhanced. Its character window is 8×14 dot matrix, and the character display quality is better than CGA and close to MDA.
- VGA (Video Graphics Array) standard: In the character mode of the VGA standard, the character window is 9×16 dot matrix, and the resolution is 640×480 pixels and 16 colors in the graphics mode, or 320×200 pixels and 256 colors. There's also a text mode at 720 x 400 pixels.

printing device

Dot matrix dot matrix printer: simple structure, small size, light weight, low price, unlimited character types, easy to print Chinese characters, and can also print graphics and images.
Laser printer: It adopts laser technology and photographic technology, with good printing quality and wide application.
Inkjet printer: It is a serial non-impact printer. The printing principle is to spray ink onto ordinary printing paper. If red, green and blue three-color inkjet heads are used, color printing can be realized.

5.3 I/O connectors

5.3.1 I/O interface overview

An interface can be regarded as the interface between two systems or two components. It can be a connection circuit between two hardware devices or a common logical boundary between two softwares.

The reason for setting the interface is as follows:

A machine is usually equipped with multiple I/O devices, each of which has an English device number (address), and the selection of I/O devices can be realized through the interface.
There are many types of I/O devices with different speeds, which may be very different from the speed of the CPU. Data buffering can be realized through the interface.
Some I/O devices may transmit data serially, while the CPU generally transmits data in parallel, and the data string-to-parallel format conversion can be realized through the interface.
The input and output levels of I/O equipment may be different from the input and output levels of the CPU, and the level conversion can be realized through the interface.
When the CPU starts the work of the I/O device, it needs to send various control signals to the I/O device, and control commands can be transmitted through the interface.
The I/O device needs to report its working status to the CPU in time. The working status of the device can be monitored through the interface, and the status information can be saved for the CPU to query.

5.3.2 Function and composition of interface

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As shown in the figure above, it is a computer with a bus structure, and each I/O device is connected to the system bus through an I/O interface. The I/O bus in the figure includes data lines, device selection lines, command lines and status lines.

According to the reasons for setting the interface above, it can be concluded that the outgoing interface should generally have the following functions and corresponding hardware configuration:

Site selection function: when the equipment code on the equipment selection line matches the equipment code, the equipment selection signal SEL should be sent;
The function of transmitting commands: Usually, a command register and a command decoder for storing commands are set in the I/O interface to respond to the commands of the CPU.
The function of transmitting data: the interface usually has a data buffer register (Data Buffer Register, DBR), which is used to temporarily store the information to be exchanged between the I/O device and the host, and is connected to the data line in the I/O bus.
The function of reflecting the working status of I/O devices: In order to enable the CPU to know the working status of each I/O device in time, some triggers reflecting the working status of the devices must be set in the interface.

5.3.3 Interface type

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Classified by data transfer method:
- Parallel interface: transfer all bits of a byte (or a word) at the same time;
- Serial interface: one bit is transmitted between the device and the interface. Since the interface and the host are transmitted in parallel in bytes or words, for the serial interface, there must be a serial-to-parallel conversion device inside. .
Categorized by flexibility in function selection:
- Programmable interface: its function and operation mode can be changed or selected by program;
- Non-programmable interface: Its function cannot be changed by the program, but different functions can be realized through hard-wired logic.
Classified by generality:
- Universal interface: available for a variety of I/O devices;
- Dedicated interface: specially designed for a certain type of peripheral or a certain purpose.
Classified according to the control method of data transmission:
- Programmatic interface: used to connect to slower I/O devices, such as display terminals, keyboards, printers, etc.;
- DMA type interface: used to connect high-speed I/O devices, such as disks, tapes, etc.

5.4 Program query method

5.4.1 Program query process

Single IO device

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Multiple IO devices

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5.4.2 Interface circuit of program query mode

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Taking the input device as an example, the working process of this interface is as follows:

When the CPU activates the input device through an I/O command, the device code field of the command is sent to the device selection circuit through the address line.
If the equipment code of the interface matches the code on the address line, the output SEL is valid.
The start command of the I/O instruction sets the work trigger B to "1" through the "NAND" gate, and sets the completion trigger D to "0".
The operation of the device is started by the B flip-flop.
The input device sends data to the data buffer register.
The device sends a signal of the end of the device's work, and sets D to "1" and B to "0", indicating that the peripheral is ready.
The D flip-flop notifies the CPU with a "ready" state, which means "data buffer is full".
The CPU executes the input instruction, sends the data in the data buffer register to the general-purpose register of the CPU, and then stores it in the relevant unit of the main memory.

5.5 Program interruption mode

5.5.1 The concept of I/O interrupt

Interruption : When the computer is executing the program, when abnormal conditions or special requests occur, the computer stops the running of the current program and turns to the processing of these abnormal conditions or special requests. After the processing is completed, it returns to the interruption of the current program and continues Execute the original program.

5.5.2 I/O interrupt generation

When the I/O device exchanges information with the host, due to the influence of the electromechanical characteristics of the device itself, its working speed is low and cannot match the CPU. Therefore, after the CPU starts the device, it often takes a while to realize the communication between the host and the I/O device exchange of information between.

If the CPU does not wait meaninglessly while the device is preparing, but continues to execute the current program, only when the I/O device is ready to make a request to the CPU, then temporarily interrupt the current program of the CPU and transfer to the I/O service program, which will cause I/O interrupt.

5.5.3 Interface Circuit of Program Interrupt Mode

In order to handle I/O interrupts, relevant hardware lines must be configured in the I/O interface circuit:

Interrupt request trigger and interrupt mask trigger: Each external device must be configured with an interrupt request trigger INTR. When it is "1", it means that the device makes an interrupt request to the CPU. But when the device wants to make an interrupt request, the device itself must be ready, that is, the state of the completion trigger D in the interface must be "1".
Queueer: When multiple interrupt sources make requests to the CPU at the same time, the CPU can only queue them according to the different nature of the interrupt sources, give different levels of priority, and respond according to the priority level.
Interrupt vector address forming part (device encoder): Once the CPU responds to the I/O interrupt, it must suspend the current program and go to execute the interrupt service program of the device. Different devices have different interrupt service routines, each service routine has an entry address, and the CPU must find this entry address.

Note :

As far as I/O interrupts are concerned, the higher the speed of the I/O device, the higher the priority, because if the CPU does not respond to the high-speed I/O request in time, its information may be lost immediately.

5.5.4 I/O interrupt processing

The conditions and time for the CPU to respond to interrupts

The condition for the CPU to respond to the interrupt request from the I/O device must be "1" to allow the interrupt trigger EINT in the CPU to be satisfied. The flip-flop can be set by the interrupt command (called interrupt on); it can also be automatically reset by the interrupt command or hardware (called interrupt off).

The time for the CPU to respond to interrupts must be at the end of each instruction execution phase.

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I/O interrupt handling process

The interrupt handling process can be divided into five phases:

interrupt request
interrupt arbitration
interrupt response
interrupt service
interrupt return

Specific location:

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The CPU sends the command to start the I/O device, and the B in the interface is set to "1", and the D is set to "0".
The interface enables the input device to start working.
The input device sends data into the data buffer register.
The input device sends a "device work end" signal to the interface, and sets D to "1" and B to "0", indicating that the device is ready.
When the device is ready (D=1), and the device is not masked (MASK=0), at the end of the instruction execution phase, the CPU sends an interrupt query signal.
The device interrupt request trigger INTR is set to "1", which indicates that the device makes an interrupt request to the CPU . At the same time, INTR is sent to the queue for interrupt arbitration .
If the CPU allows interrupts (EINT=1), the device is queued and selected again, that is, it enters the interrupt response stage , and the interrupt response signal INTA sends the output of the queue to the encoder to form a vector address.
The vector address is sent to the PC as the address of the next instruction.
Since an unconditional transfer instruction is stored in the vector address, after the execution of this instruction is completed, it will unconditionally transfer to the service program entry address of the device, start to execute the interrupt service program, enter the interrupt service stage, and buffer the data through the input instruction The input data of the register is sent to the general-purpose register of the CPU, and then stored in the relevant unit of the main memory.
The last instruction of the interrupt service routine is the interrupt return instruction. When its execution ends, the interrupt returns to the breakpoint of the original program.
So far, a complete program interrupt processing process has come to an end.

5.6 DMA mode

5.6.1 Features of DMA mode

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It can be seen from the figure that since there is a data path between the main memory and the DMA interface , when exchanging information between the main memory and the device, the CPU is not used, and the CPU does not need to suspend the current program to serve the device, eliminating the need to protect the site and restore the site , so the working speed is higher than that of the program interrupt mode.

In the DMA mode, since the DMA interface shares the main memory with the CPU, there may be a conflict between the two competing for the main memory. In order to effectively use the main memory in time-sharing, the following three methods are usually used when DMA exchanges data with the main memory:

Stop the CPU from accessing main memory:
- Method: When the peripheral device requests to transmit a batch of data, the DMA interface sends a stop signal to the CPU, requiring the CPU to give up the right to use the address line, data line and related control lines. After the DMA interface obtains the bus control right, it starts data transmission. After the data transmission is completed, the DMA interface notifies the CPU that the main memory can be used, and returns the bus control right to the CPU.
- Advantages: simple control, suitable for I/O devices with high data transmission rate to realize group data transmission.
- Disadvantage: When the DMA interface accesses the main memory, the CPU is basically in a non-working state or remains in the original state.
Cycle Stealing (or Cycle Stealing):
- Method: In this method, whenever the I/O device issues a DMA request, the I/O device embezzles or steals the bus occupancy for one or several main memory cycles, and when the DMA does not request, the CPU continues to access the main memory .
- Advantages: This method not only realizes I/O transmission, but also better utilizes the efficiency of main memory and CPU, and is a widely used method.
- Disadvantages: It is more suitable for the case where the read/write cycle of the I/O device is greater than the main memory cycle, and it is not recommended for other cases.
DMA and CPU alternate access:
- Method: The process of application, establishment and return of the bus usage right is not required, and the bus usage right is controlled by C1 and C2 respectively. The CPU and DMA interfaces each have independent access address registers, data registers and read/write signals.
- Advantages: The CPU neither stops the operation of the main program nor enters the waiting state, that is, completes the data transmission of the DMA, and has high efficiency.
- Disadvantages: The corresponding hardware logic is complex.

5.6.2 Function and composition of DMA interface

Functions of the DMA interface

When using DMA to transfer data, the DMA interface should have the following functions:

Apply for DMA transmission to the CPU.
When the CPU allows DMA to work, it handles the transfer of bus control rights to avoid affecting the normal activities of the CPU or causing bus competition due to entering the DMA work.
Manages the system bus and controls data transfers during DMA.
Determine the start address and data length of data transmission, and correct the data address and data length during data transmission.
At the end of the data block transfer, the DMA operation is signaled to be complete.

Basic composition of DMA interface

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Main memory address register (AR): used to store the address in main memory that needs to exchange data.
Word Counter (WC): It is used to record the total number of words of the transmitted data, and is usually preset with the complement value of the number of exchanged words.
Data buffer register (BR): used to temporarily store the data transmitted each time.
DMA control logic: Responsible for managing the DMA transfer process, consisting of control circuits, sequential circuits, and command status control registers.
Interrupt mechanism: When the word counter overflows (all "0"), it means that a batch of data exchange is complete, and the "overflow signal" sends an interrupt request to the CPU through the interrupt mechanism, requesting the CPU to perform post-processing of the DMA operation.
Device address register (DAR): store the device code of the I/O device or indicate the addressing information of the device information storage area, such as the area number and cylinder number of the disk data.

5.6.3 DMA working process

The data transfer process of DMA is divided into three stages:

preprocessing
data transmission
Post-processing

preprocessing

Indicates to the DMA control logic whether the data transfer direction is input (write main memory) or output (read main memory).
Send the device number to the DMA device address register and start the device.
Send the main memory start address of the exchanged data to the DMA main memory address register.
Assign the number of exchanged data to the word counter.

data transmission

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Post-processing

When the DMA interrupt request is responded, the CPU stops the execution of the original program, turns to execute the interrupt service routine, and executes the end work of the DMA:

Verify that the data sent to the main memory is correct;
Decide whether to continue to use DMA to transfer other data blocks. If you continue to transfer, you must initialize the DMA interface. If you do not need to transfer, stop the peripherals;
Test whether there is an error in the transmission process, if there is an error, turn to the error diagnosis and error handling program.

5.6.4 Types of DMA Interface

Selective DMA interface

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Features :

Multiple devices can be connected physically, but only one device can be connected logically, that is, the DMA interface can only serve one device within a certain period of time;
The key is to send the device number of the selected device into the device address register during preprocessing.

Multiplexed DMA interface

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Features :

The multi-channel DMA interface can not only connect multiple devices physically, but also allow multiple devices to work at the same time logically. Each device uses byte interleaving to transmit data through the DMA interface.
This type of interface is particularly suitable for simultaneously serving several devices with not very high data transmission rates.