An instruction format
Instruction: code opcode field address field
Instruction word (referred to as instruction): indicates a machine word instruction.
Instruction format: a command structure represented with binary code occupied by the operation code field and an address code fields.
Opcode Field: Characterization of operating characteristics and functions of the instruction ( to uniquely identify instruction ) can not be different from the same instruction opcodes
Address code fields: the address codes specify the operand involved in the operation
Second, the opcode category
Operation code can be divided into variable length codes and the code length of the fixed
1, fixed-length code
There are multiple equal-length instruction operation code
For example: a computer of a total of 64 instructions, uses fixed-length operation code requires six coding, from the 6th power of 000,000 ~ 1,111,112 64
Advantages: simple encoding method, decoding the instruction to facilitate
OK: inconvenient to add a new instruction command (extended convenient)
2, the variable-length code
Unequal opcode may reduce the average length of the operating code, to improve the efficiency of instruction code, the instruction from the scalability perspective, but also desired variable length operation code.
For example: a computer 100 is provided instructions, requirements:
1) fixed length code encoding operation, which is designed to make the operation code encoding
2) It is assumed that the instructions 100 use instructions 10 changed to 90%. The remaining 90 instruction using the probability reaches 10%, use of variable length coding scheme designing a coding operation code, and to determine the average length of the operating code (common short code with the instruction by the instruction length coding is not used)
A, 1) fixed length code encoding operation, a 7-bit opcode, which take as an operation code 100 codes between the code 0000000 ~ 1100011 Representative instructions 100 (a length of 7)
Total 1111111 1100100 ~ remaining 28 codes can be used to add new opcodes
2) no code encoding operation using a fixed length code may be four instructions 10 encodes 8-bit instruction code encodes 90
0000 ~ 1001 corresponding to the common command 10, 1010 through 1111 back never use spreading code 4
16 10,101,111 10,100,000 -
10110000 ~ 10111111 16
16 11,001,111 11,000,000 -
11010000 ~ 11011111 16
11100000 ~ 11101111 16
11110000 ~ 11111001 10
1010 has 90 code represented between 0000 1111,1001 on the remaining instructions 90
The average length of the instruction operation code is:
4 8 * * 90% + 10% = less than 4.4 as long as the encoded 7
The remaining coding 1111111 11111010 ~ (6) can be used for further operation of spreading code length
Example: the computer is provided with a simple instruction a total of 10 instructions, each instruction frequency is as follows:
11 20% 12 12% 13 11% 14 15% 15 8% 16 3% 17 2% 18 18% 19 10% 110 1%
1) using Huffman coding Design This instruction operation code 10, and the average length of the operating code
2) Design 2 only in length, and an average length of no greater than 3.20 as long as the extended opcode, and calculate the average length of the opcode
A: 1) Huffman tree
The Huffman encoding result represents 0 :( left branch and right branch represents 1 side from the last Huffman coding follows the start 0.20)
11 011 010 001 101 100 0001 00001 000001 000000
Average length: 0.2 + 3.03 = 2 * 3. * - 18 + 0.15 * 3 + ....
2) one design is to take 3 and 4 in two lengths, such as 000 001 010 011 100 1,011,100,110,111,101,111
The average length of 3.14
3 can represent eight kinds of coding, we choose to represent three coded 7, left 4 needs to be extended is the need 2
Another design is to select two lengths 3 and 5, such as: 000001010011 11110 1,001,011,101,110,011,101
The average length of 3.12
Select 3 and 7 showing the front fixing extension 111 3 2 4 2 is the power of 2> 3 satisfies
Third, the address code
Field specifies the instruction operand storage location address codes is called, the address code may include a memory address. It may also include a register number.
Instruction may have one, two, or three operands, the operands can not, there are several operand address, instructions may be divided into an instruction according to the instruction at address zero. An instruction address, the instruction address of two, three-address instruction. Instruction 4 address codes are rarely used.
| Operation code field | address code | |||
| Opcode | A1 | A2 | A3 | Three address instruction |
| Opcode | A1 | A2 | Two instruction address | |
| Opcode | A1 | An instruction address | ||
| Opcode | Instruction address zero | |||
Zero-address instruction: operation code only, no address code (no operation stop)
One address instruction: only one instruction code address code indicating the storage location of an operand participate in the operation, if there is the other operand is implied in the accumulator
eg: INC AL
INC [S1]
Two address instruction: instruction code has two addresses, each storage location number indicated two operation to operation, the result is stored in an address in which
(On a1, a2: a1 a2 in a1)
eg: MOV AL, BL
ADD AL, 30
Three-address instruction: instruction code has three address code indicating the address of the storage location of an operand to operation and a result of the two
(Op a1, a2, a3: a1 op a2 a3)
Two address instruction format, there are three types can be classified from the physical location of the operand is
Register - register (RR) type instruction: a plurality of general purpose registers or individual needs special purpose registers, operand fetch from the register, the operation result into another register, the machine to perform Register - register type instruction is very fast, does not require access memory .
Register - a memory (RS) type instructions: when executing such instructions, it is necessary to access the memory cells, but also access registers.