1. Create a project

Create Project:

Next：

Fill in the project name, select the project location, Next:

Select the RTL project, check it Do not specify sources at the time, that is, do not add source files, Next:

Select chip type, Next:

Finish：

2. Add Verlog design files

1. Add tv file

Add Sources：

Choose the second one, Next:

Create File：

Select the file type, fill in the file name, OK:

Finish：

Define the input and output ports of the module, do not set it temporarily, directly OK:

2. Write the document

Double-click to open the file:

write:

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2022/09/10 16:06:39
// Design Name: 
// Module Name: t
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module t(
    input   wire    a,
    input   wire    b,
    
    output  wire    c,
    output  wire    d,
    output  wire    e,
    output  wire    f
);

    assign c = ~a;
    assign d = a & b;
    assign e = a | b;
    assign f = a ^ b;


endmodule

3. Add simulation files

1. Add t_tb.v file

Add a simulation file and fill in the name:

OK：

Yes：

2. Write the document

open a file:

write:

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2022/09/10 16:48:54
// Design Name: 
// Module Name: t_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module t_tb(

    );
    
    parameter   CYCLE   =   20;
    
    reg     clk;
    
    reg     a;
    reg     b;
    
    wire    c;
    wire    d;
    wire    e;
    wire    f;
    
    
    always #(CYCLE / 2) clk = ~clk;
    
    initial begin
        clk = 0;
        a = 1'b0;
        b = 1'b0;
        repeat(10) begin
            a = {
    
    $random};
            b = {
    
    $random};
            # (CYCLE * 5);
        end
        
        $finish;
    end
    
    
    t t_t(
       /*input   wire*/  .a(a),
       /*input   wire*/  .b(b),

       /*output  wire*/  .c(c),
       /*output  wire*/  .d(d),
       /*output  wire*/  .e(e),
       /*output  wire*/  .f(f)
    );
    
endmodule