vivado three voting simulation

Outline

The following three voting circuit simulation with verilog to look at the use of vivado software.

Preparation of design documents

First, you can create new project to create a new interface by the beginning of the project, it can also file-->project-->new...be a new project

Click next

Then give the file a name, see the name of the best-known Italian

At first we do not need to add the source file through the program, so the hook can hook

Like the corresponding default selection device

Click Finish on the new project a success

Click the plus source in the panel, as a new right half of the three file, i.e. constraint file, the source (design) file, simulation file, where a new first source file.

Click to create file file name, path, and language settings, where you can set only the name of the design file.

Click Finish.

Here we want to set the input and output port settings file, we can in this set, you can also write your own code.

In the source panel, double-click the file to see its source code where I had been prepared, according ctrl Ssave, source file, error file does not appear, that indicates that writing code is correct

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module srbj( input a, input b, input c, output d ); assign d=a&b|a&c|b&c; endmodule

Examples of errors:

Click on the left side RTL ANALYSIScan generate relevant logic diagram, check whether there is a logical problem

Write simulation files

Similarly the new simulation files, without having to set the input and output ports

Write code as follows

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srbjsimu Module1; REG A, B, C; // three registers Wire D; srbj SL (A, B, C, D); // instantiate three voting source file object Initial the begin A = 0; B = 0; = C 0; // initial value 0 End Always # 10 {A, B, C} = {A, B, C} + 1; // every delay 10, to be added to an abc, i.e. in the 0-7 inter circulation endmodule

Click on the left RUN　Simulationto view simulation results

Click the two buttons shown may be adjusted to the proper view

FIG complete the following, the frame can view the position where each of the input and output time by dragging yellow.