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When using the simulator that comes with Vivado, there is no need to compile the simulation library, the simulation library itself exists, it is here, as shown in the figure below , but when using a third-party simulator, it is necessary to compile a special simulation library for the simulator. These simulation libraries include models such as component and IP shape, timing, etc. It is impossible to not compile, but you only need to compile it once when you start to use it.
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The VHDL and Verilog catalogs in the above figure have descriptions of many basic components. When a project wants to get rid of the dependence on a company's devices, it is intended to start with the description of the basic components, such as registers, flip-flops, etc., which can be directly modified. Pay attention to the path of the file
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When compile_simlib is Questasim compiled libraries with Vivado library-building tools, will build the library directory (such as on <questasim_install_dir> \ xilinx_lib) to generate the next modelsim.ini file, this file in the following figure , the file referenced in the statement of the library All have been automatically generated and can be copied directly to Questasim's own modelsim.ini (in <questasim_install_dir>\), which is much more convenient than writing by yourself.
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There are two ways to generate the library: one is to use Vivado's IDE, and the other is to use TCL commands.
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VHDL language does not have simprim library, this should be noted, as shown below
- RTL-level simulation, post-synthesis functional simulation, post-synthesis timing simulation, post-realization functional simulation and post-realization timing simulation require different library support, as shown in the figure below
- As for the role of each library and other details, you can refer to UG900