When developing FPGA projects, it is often necessary to use third-party simulation tools for simulation. It will be troublesome if the third-party simulation tools need to be called from Vivado every time. Recently, we summarized the previous methods of building a simulation environment without vivado, and wrote a practical software. This article will share with you how to use the software, hoping to help you. The software was developed by classmate Shi Tingao. There is a software download link at the end of the article.
development purpose
In the process of FPGA project development, it is necessary to complete operations such as design code development, verification environment construction, simulation analysis, and board-level verification. In this process, although many operations are essential, the steps are repeated. The auxiliary software uses Python auxiliary software to simplify some repetitive and complex operations through predefined processing modes to improve project development efficiency. Independent simulation can simplify the simulation steps without relying on Vivado, but establishing independent simulation often requires complicated and tedious steps, so it is necessary to simplify the steps of establishing independent simulation.
The important thing is that there is a separate environment from the third-party simulation tools built by Vivado. The simulation environment is built in advance for the subsequent ASICization of the FPGA project. Only the libraries and related files used are extracted from the Vivado library. At the same time, each time During simulation, there is no need to start the resource-intensive Vivado software, just run the simulation script directly. At the same time, the simulation environment generated by the software can also be manually optimized and adjusted, and customized modifications can be made according to the user's familiar simulation habits.
Function description
This software is used to improve FPGA simulation efficiency and save simulation time and steps. This software can establish independent simulations and generate independent simulations in Questasim, modesim or VCS environments. The visual interface makes it more convenient for users to operate.
After the RTL design is completed, simulation will be carried out. Vivado has its own simulator, or you can start joint simulation with third-party simulation tools through Vivado. However, in the actual project development process, when we modify the code, we need to close the simulation software and restart the simulation, and the previously loaded waveform signal also needs to be reloaded. Therefore, many times, we hope to break away from Vivado and use third-party simulation tools such as Modelsim or VCS to improve simulation efficiency; in this process, by extracting the code files and IP core information files in the project, we can reduce the memory space occupied by the project, which is convenient Project developer synchronization and backup. To establish an independent simulation, the software will first extract the source simulation tool and the destination simulation tool to understand which environment to establish an independent simulation. It is also necessary to extract the name of the automated simulation file and the path to create an independent simulation, which is used to create an independent simulation folder. This folder has two folders, rtl and sim, and the files used in the simulation will be placed in this folder. Then it will extract the module name of tb and the path of the do file generated by vivado. The software will find the do file generated by Vivado based on the path and the module name of tb, extract the information in the do file, and put the corresponding file into the automated simulation folder. Extract the path to the win64 and .setup files of the target simulation tool, which is used to create batch files and makefile files. After extracting the information, click the "Start Generation Button" to complete the automated simulation operation.
This software can be run in an executable python environment. In actual project testing, it can automatically generate automated simulation projects, reduce the simulation's dependence on vivado, and reduce a large number of repetitive operations.
In order to facilitate the use of auxiliary software by project developers, the auxiliary software needs to have a good visual operation interface. After completing the configuration of some basic parameters, complex operations can be completed with one click. The GUI interface is shown in Figure 1:
Instructions for use
1 Installation and initialization
This software requires no installation and can be executed by clicking on the FPGA_simulate_tool.exe file, as shown in Figure 2:
2 input
Enter the command to be executed according to the prompts on the GUI interface.
3 output
After running the software, different output files will be generated first according to the selection. Select "Automated Simulation Generation Tool". After entering the prompt information, click "Start Generation" to generate the automated simulation project, as shown in Figure 3, in which all rtl files are generated. It is stored in the rtl folder, the include file is stored in the inlcud folder, and the sim file stores do files and batch files.
Steps
This software provides sample operations in the python executable environment of Windows 10. The steps to use the automated simulation generation tool are as follows:
Step 1: First select the source simulation tool and destination simulation tool. The source simulation tools available include ModeSim and Questasim, and the destination simulation tools available include ModeSim, Questasim, and VCS, as shown in Figure 7.
Step 2: Enter the name of the tb module and the name of the automated simulation file, and a folder with that name will be generated. The automated simulation project is in this folder.
Step 3: Select the "Select Path" button after "Create Independent Simulation Path", which will prompt you to select a path. After selecting, click the "Select Folder" button and choose to create an independent simulation path, as shown in Figure 8:
Step 4: Click the "Select Path" button and select the do file path of vivado and the win64 or .setup path. The overall input information is as shown in Figure 9:
Step 5: Click the "Start Generation" button to generate an independent simulation project. "PASS" will be displayed if the generation is successful. As shown in Figure 10. The independent simulation project directory is in the D drive folder "bus0123_40_25_NO_UDP_1", and the file name is "2". The contents of this folder are shown in Figure 11, in which all rtl files are under the rtl folder, and all include files are under the include folder. When the destination simulation tool selects "modelsim" or "questasim", the contents of the sim folder are as shown in Figure 12. The .coe file is the initialization file of the RAM of the source vivado project, not the file generated by the software. The filelist.f file stores all RTL lists that need to be compiled. The run.do file is used for automated simulation. sim.bat and sim_fast_no_gui.bat are batch files. The above four files are generated by the software. Click sim.bat or sim_fast_no_gui.bat to run the simulation tool for automated simulation. Among them, sim_fast_no_gui.bat eliminates the GUI interface of the simulation tool and can speed up the simulation speed. When the destination simulation tool selects "VCS" ( although Vivado has its own one-click conversion to VCS simulation function when combined with VCS simulation, the software in this article provides a more direct way to detach, and combine the used libraries and all Extract the files separately and put them into a folder for easy sharing and creation of the necessary environment for ASIC IP replacement ). The contents of the sim folder are shown in Figure 13. The .coe file is the initialization file of the RAM of the source vivado project, not the file generated by the software. The filelist.f file stores all RTL lists that need to be compiled. Makefile is an automatic simulation file. Enter make to perform automatic simulation of VCS. After the simulation is completed, enter make verdi to open the waveform file with verdi.
Double-click the sim.bat file in the picture above to run it.
Note: It is recommended to run the software on the machine where the original Vivado project is located to extract relevant script information. The original Vivado project needs to call a third-party simulation tool to run it and retain the corresponding sim folder. If you have any questions, please check the vivado version and simulation tool version, as well as the vivado version and simulation tool version used by the compiled vivado simulation library.
in conclusion
Based on predefined Python script commands, this software inputs necessary information through user interaction with the GUI interface, and simplifies the originally repetitive and cumbersome operations through auxiliary software, improving the efficiency of RTL simulation. By batch processing a large number of repetitive files and folders, this software reduces the tedious operations of manually creating folders, writing repetitive codes, and manually converting table items. In addition, through interaction with the GUI interface, a visual interface is provided, which greatly improves the operability of the software.
Baidu Netdisk download link of the software:
Link: https://pan.baidu.com/s/1b7VeRU8FaNBn93aWVaGFAQ
Extraction code: ccu6
Everyone is welcome to leave a message to exchange experience and questions.
Author: Shi Tingao
Editor in charge: Pan Weitao