The following is some knowledge that I often encounter in the design of PCIe, and I have briefly sorted them out, including basic definitions, transmission rates, layout requirements, etc. For example, as a hardware engineer, you need to understand the chip architecture, which PCIe interfaces can be used, what to do with these PCIe, whether to use PCIe x1 or x2, etc. After the hardware engineer finishes designing the interface, the layout engineer gets the schematic diagram and starts PCB design. That involves the layout design requirements of PCIe, including impedance, layout length, and the number of vias. After the layout design is completed, in order to ensure the quality of the signal, a signal integrity simulation is required for this high-speed signal to check whether the layout meets the requirements. At this time, it is necessary to build a PCIe simulation link, which may require IBIS, PCB S parameters, SI specs, etc.
1. Basic definition of PCIe:
PCI-Express (peripheral component interconnect express) is a high-speed serial computer expansion bus standard. PCIe is a high-speed serial point-to-point dual-channel high-bandwidth transmission, and the connected devices are allocated exclusive channel bandwidth. PCI Express also has a variety of specifications, from PCI Express x1 to PCI Express x32, which can meet the needs of low-speed devices and high-speed devices that will appear in a certain period of time in the future. The PCI-Express interface is a PCIe 3.0 interface with a bit rate of 8Gbps, which is about twice the bandwidth of the previous generation of products, and includes a series of important new functions such as transmitter and receiver equalization, PLL improvement, and clock data recovery. To improve data transmission and data protection performance. A PCI Express bus link supports full-duplex communication between any two endpoints.
2. PCIe channel:
The channel (lane) consists of two differential signal pairs, one for receiving data (RX), the other for transmitting data (TX), and a pair of differential reference clocks (CLK). Therefore, each channel consists of four wire data lines. Conceptually, each lane acts as a full-duplex byte stream, transmitting packets in 8-bit "byte" format simultaneously in both directions between the link endpoints. A physical PCI Express link may contain from 1 to 32 lanes, more precisely 1, 2, 4, 8, 12, 16 or 32 lanes. Channel counts are prefixed with an "×" (e.g. "×8" for an eight-channel card or slot), with ×16 being the largest size commonly used.
3.Mini PCIe:
A PCI Express Mini Card based on PCI Express (also known as Mini PCI Express, Mini PCIe, Mini PCI-E, mPCIe, and PEM) is an alternative to the Mini PCI form factor. Mini PCI-E connector, this product is widely used in notebook computer motherboards, such as E-PC, Netbook, and wireless network cards, solid state drives and other equipment. Pin definition:
4. PCIe version:
On January 12, 2022, the PCI-SIG organization officially released the PCIe 6.0 standard, with a speed of 64 GT/s. On June 22, 2022, the alliance PCI-SIG, which publishes and maintains the PCIe standard, announced the launch of the latest generation of PCIe specification PCIe 7.0 or PCIe Gen 7. The latest generation of PCIe doubles the bandwidth to achieve 128GT/s or 128Gbps aggregate throughput unidirectionally on one lane (x1).
5. PCIe encoding method:
6. Unit:
GT/s: Giga Transmission per second, Giga Transmission per second, the number of transmissions per second.
Gbps: Giga Bits Per Second, gigabits per second.
There is no proportional conversion between GT/s and Gbps.
1GB/s = 8Gbps = 8Gbit/s
bit bit: Bit is the smallest unit of data stored in a computer, referring to a bit in a binary number, and its value is "0" or "1".
byte Byte: A byte is the basic unit of computer storage capacity, and a byte is composed of 8-bit binary numbers.
7. PCIE bandwidth calculation
Throughput = transmission rate * encoding scheme, the current PCI-e2.0 protocol supports 5.0 GT/s, that is, each Lane supports transmission of 5G Bits per second; the encoding method is 8b/10b encoding scheme, that is, every To transmit 8 Bits, 10 Bits need to be sent. Then, each Lane of the PCIe 2.0 protocol supports a rate of 5 * 8 / 10 = 4 Gbps = 500 MB/s. , a PCIe 2.0 x16 channel, the available bandwidth of x16 is 4*16 = 64 Gbps = 8 GB/s, and the bidirectional bandwidth is up to 16GB/s.
8. PCIe signal definition:
PERST# signal: This signal is a global reset signal, which is provided by the processor system, and the processor system needs to provide the reset signal for the PCle slot and the PCle device. PCle devices use this signal to reset internal logic. When this signal is valid, the PCle device will perform a reset operation. The PCle bus defines a variety of reset methods, and the realization of the two reset methods, Cold Reset and Warm Reset, is related to this signal.
WAKE# signal: When the PCIe device enters the sleep state and the main power supply has stopped, the PCle device uses this signal to submit a wake-up request to the processor system, so that the processor system can provide the main power supply Vcc for the PCIe device again.
CLKREQ# signal: A low-level active open-drain signal driven by the plug-in card, requesting that the PCI Express reference clock is available (active clock state) to allow the PCI Express interface to send/receive data.
CLK_P/ CLK_N# signal: low voltage differential signal. The system board needs to provide a reference clock
TX/RX# signal that conforms to the general architecture of the PCIe basic specification: the signal is bidirectionally transmitted;
9.PCIe Simulation:
PCIe signal integrity simulation requires pre-preparation work: chip IBIS model (IBIS-AMI), chip PKG, extracting S parameters of PCB traces, S parameters of connectors, SI Spec, etc. The following is a reference to Orin_NX_Orin_Nano_Signal_Integrity_Simulation:
10. PCIe layout requirements:
PCIe has relatively strict requirements for PCB design. The first is the requirement of differential impedance: 85/50 ohms, ±15%. There is also the maximum number of holes for wiring: 4 (Use micro via or back drilled via - no via stub allowed.) and so on. The following is the Jetson_Orin_NX_Series_and_Orin_Nano_Series_Design_Guide:
11. Reference website:
https://pcisig.com/
https://baike.baidu.com/item/pcie/2167538?fr=aladdin
https://blog.csdn.net/weixin_41808082/article/details/124377320?spm=1001.2014.3001.5501
https://developer.nvidia.com/embedded/downloads#?tx=$product,jetson_orin_nx
The above information is mainly compiled by myself in PCB design and Internet search. If there
is any similarity or error, I hope you will leave a message and correct me, thank you! ! !
