[ESP32] [Hardware Design]

1. ESP32 chip classification:

There are currently 6 types of ESP32:

Order model	Kernel	Embedded flash	Communication mode	Package	Operating temperature
ESP32-D0WD-V3	Dual-core	No embedded flash	Wi-Fib / g / n + BT / BLE dual mode	QFN 5 * 5	–40 °C ~ 125 °C
ESP32-D0WDQ6-V3	Dual-core	No embedded flash	Wi-Fib / g / n + BT / BLE dual mode	QFN 6 * 6	–40 °C ~ 125 °C
ESP32-D0WD	Dual-core	No embedded flash	Wi-Fib / g / n + BT / BLE dual mode	QFN 5 * 5	–40 °C ~ 125 °C
ESP32-D0WDQ6	Dual-core	No embedded flash	Wi-Fib / g / n + BT / BLE dual mode	QFN 6 * 6	–40 °C ~ 125 °C
ESP32-D2WD	Dual-core	16Mbit embedded flash (40MHz)	Wi-Fib / g / n + BT / BLE dual mode	QFN 5 * 5	–40 °C ~ 105 °C
ESP32-S0WD	Single core	No embedded flash	Wi-Fib / g / n + BT / BLE dual mode	QFN 5 * 5	–40 °C ~ 125 °C

V3 is the recent wafer-level improvement (ECO V3) of Espressif's ESP32 series products. The main changes are as follows:

Fix PSRAM Cache issue: Fix the "read and write exception when the CPU accesses the external SRAM in a specific order"
Fix the problem that "dual-core CPU may read errors when reading different address spaces"
In response to the customer's "ECO V1 hardware configuration, the 32.768KHz crystal oscillator cannot start normally with a small probability", optimize the stability of the external 32.768KHz crystal oscillator
Fix the fault injection problem related to "Safe Boot" and "Flash Encryption"
Optimization: The minimum bandwidth supported by the CAN module is widened from 25KHz to 12.5KHz

2. Pin function

The ESP32 pin configuration is very flexible. The screenshot from the Datasheet is as follows:

However, there are still several special functions that require specific pins, as follows:

The corresponding relationship between the built-in flash port and chip pins in ESP32-D2WD is: CS # = GPIO16, IO1 / DO = GPIO17, IO3 / HOLD # = SD_CMD, CLK = SD_CLK, IO2 / WP # = SD_DATA_0, IO0 / DI = SD_DATA_1 . These pins of the chip are not recommended for other functions
Except for ESP32-D2WD, the connection relationship between the ESP32 chip and the external flash data port is: SD_DATA0 / SPIQ = IO1 / DO, SD_DATA1 / SPID = IO0 / DI, SD_DATA2 / SPIHD = IO3 / HOLD #, SD_DATA3 / SPIWP = IO2 / WP ##

GPI34 ~ GPI39 can only be used as input function;
It is recommended to use ADC1, it is recommended to add a 0.1uF capacitor close to the ADC function pin;
2 * 8 bit DAC can only be assigned to: GPIO25 and GPIO26
The drive strength of the digital output pins can be configured in four gears:
- 0 ： 5mA
- 1： 10mA
- 2: 20mA (default)
- 3： 40mA

2.1 VDD_SDIO：

The maximum output current of VDD_SDIO is 40mA.
When VDD_SDIO is 1.8V output, the voltage range is 1.65V ~ 2.0V, and it is necessary to add 2K // 4.7uF circuit close to its pin.
When VDD_SDIO is 3.3V output, it is powered by VDD3P3_RTC through 6R resistor, so the voltage is slightly lower than VDD3P3_RTC. Need to add 1uF capacitor close to its pin.

2.2 VDD3P3（Pin3&Pin4）：

Add LC filter circuit, L rated current must be 500mA or above

2.3 RF RF:

ESP32 (6x6) and (5x5) RF pin output impedances are 30 + j10 and 35 + j10, respectively, π-type matching network needs to be added during design, CLC structure is recommended
RF trace needs to do 50R impedance control;

2.4 UART：

A 499R resistor in series near U0TXD is used to suppress 80MHz harmonics;

3. Hardware design

3.1 Power-on and reset sequence:

VDD3P3_RTC Min： 2.3V
VIL_nRST ： 0.6V (max)
t0: Delay time when the CHIP_PU pin is powered on later than the system power 3.3V, the minimum value is 50us
t1: Time when CHIP_PU level is lower than VIL_nRST, the minimum value is 50us

3.2 Strapping pins:

Relationship between the establishment and holding time of CHIP_PU and strapping pins:

VIH: High-level input voltage, 0.75xVDDIO (I / O power supply) <VIH <VDDIO + 0.3
t0: CHIP_PU setup time before power on, minimum value 0ms
t1: CHIP_PU hold time after power on, minimum 1ms

ESP32 has 5 strapping pins: GPIO0, GPIO2, GPIO5, GPIO12, GPIO15.

Built-in LDO (VDD_SDIO) voltage:

Pin	default	3.3V	1.8V
GPIO12	drop down	0	1

System startup mode:

Pin	default	SPI boot mode	Download startup mode
GPIO0	pull up	1	0
GPIO2	drop down	Irrelevant	0

During system startup, control U0TXD printing:

Pin	default	U0TXD prints normally	U0TXD does not print after power on
GPIO15	pull up	1	0

SDIO slave signal input and output timing:

Pin	default	Sample on falling edge, output on falling edge	Sample on falling edge, output on rising edge	Rising edge sampling, falling edge output	Rising edge sampling, rising edge output
GPIO15	pull up	0	0	1	1
GPIO5	pull up	0	1	0	1

"VDD_SDIO" and "SDIO slave signal input and output timing" can be modified by register after power on
ESP32-D2WD has a built-in flash operating voltage of 1.8V. GPIO12 needs to be pulled high when power is turned on

4. Design considerations:

4.1 Avoid connecting the ESP strapping pins to the output pins of the peripherals (that is, the input to the ESP): the output pins of the peripherals may pull the state of the ESP strapping pins during power-on, affecting the power-on logic.