- The devices selected for producibility design must meet the company's production process requirements
Now Kangxun’s surface-mount devices can be packaged in the smallest 0402 package, and devices with packages smaller than 0402 cannot be selected, otherwise Kangxun cannot produce them; the center distance between the lead wires of QFP devices must not be less than 0.4mm, and the point distance of BGA devices must not be less than 0.5mm. The weight of the device should not exceed 25g, and the size should not exceed 55x55mm. Otherwise, Kangxun cannot process and produce. For general digital veneers, it is recommended to select devices in 0603 package.
Electrostatic discharge (ESD) can cause great damage to electronic components. When selecting devices, fully consider the electrostatic level of the Kangxun production line, and try to use devices with high anti-static levels.
For single boards with double-sided soldering, try to use SMD devices when selecting devices, reduce the number of plug-in devices, and use double-sided reflow technology as much as possible to avoid inconvenience to the soldering of plug-in devices. For the single board with double-sided reflow process, the B side (the side where the small device is placed) is generally reflow soldered first, and then the A side is assembled and soldered in reverse. When the A side is soldered, the flux of the B side device is melted at the same time, and the device is adhered by surface tension. In order not to drop the chip during soldering, do not place a device with a size larger than 12x10x5mm and less than 8 pins on the B side (the data comes from the productivity part of the new employee training materials in 2005). It is generally believed that the device on the B side should meet the weight per unit area not exceeding a certain value to ensure the processing quality: for BGA packaged devices, it should not exceed 0.13 grams per square millimeter; for QFP packages, it should not exceed a certain value per square millimeter Not to exceed 0.3 grams. When PCB layout, please consult the company's process technicians to ensure the processability of the board
Electrostatic sensitive devices should be used with caution, if used, anti-static protection measures should be added
Clarify the ESD control level of the production and assembly site, and thus put forward the ESD level requirements of the device, as the basis for type selection and ESD protection design. RF devices are extremely sensitive to ESD and generally must be produced on dedicated lines.
With the development of technology, high-density integrated circuits have become indispensable devices in the electronics industry. This kind of device has the characteristics of short line spacing, thin line, high integration, fast operation speed, low power, low withstand voltage and high input impedance, which makes this type of device more and more sensitive to static electricity, which is called electrostatic sensitivity ( ESDS) devices. The energy of electrostatic discharge (ESD) has little effect on traditional electronic components, and it is difficult for people to notice it. However, in these high-density integrated circuit components, whether it is a MOS device or a bipolar device, it may be caused by the electrostatic electric field and electrostatic discharge current. Cause failure, or cause "soft breakdown" phenomenon that is difficult to be found by people, leaving potential hidden dangers to the single board or system, directly affecting the quality, life, reliability and economy of electronic products. Let's briefly talk about how we should deal with electrostatic sensitive components in our design.
In the design of devices and products, the idea of electrostatic protection should be fully reflected, and electrostatic protection components (ESD) should be installed inside the device, and devices that are not sensitive to static electricity should be used as much as possible and appropriate protection should be provided for the electrostatic discharge sensitive (ESDS) devices used. input protection to make it more reasonable to avoid ESD damage. MOS technology is the leading technology of integrated circuit manufacturing, with metal-oxide-semiconductor field effect transistor as the basic structural element. Since the gate and source of the field effect transistor of the MOS device is a layer of submicron insulating gate oxide layer, its input impedance is usually greater than 1000M?, and it has an input capacitance of about 5pF, which is easily damaged by static electricity. Therefore, a resistor-diode protection network is set in the input stage of the MOS device, the series resistor can limit the peak current, and the diode can limit the instantaneous peak voltage. Common protective components in the device are: capacitors, bipolar transistors, silicon controlled rectifiers (SCR), etc. When ESD occurs, they react quickly before the protected device, absorb and release the energy of ESD, so that the impact of the protected device is greatly reduced. Under normal circumstances, the protective element works in its first breakdown (First Breakdown) zone and will not be damaged by ESD. Once the applied voltage or current is excessive (Overstress), the protective element entering the secondary breakdown (Secondary Breakdown) zone will be irreversibly damaged. The damage to the device loses its protective effect. When designing the whole product, you can add a suppression circuit or an isolation circuit at the most vulnerable pins of the ESDS device (such as Vcc and I/O pins), according to the electrical characteristics of the protected circuit and the available board space. Such as TVS devices, optocouplers, etc.
Hardware developers should understand the three models of electrostatic discharge: human body model, device discharge model, and machine model, and pay attention to avoiding ESD damage to devices.
Electrostatic sensitive devices must be protected by appropriate measures during storage and transportation, and stored in antistatic bags.
In addition, the anti-static design of the production environment is also the key to ESD control. The company has specially established a radio frequency production line with a high level of electrostatic protection.
The table below is the company's description of the electrostatic sensitivity level, and the information comes from "Q/ZX 12.209-2005 Lead-free Component Certification Technical Requirements".
HSDS Static Sensitivity Level Instructions
| Special (I) class |
0～500V |
| Special (II) class |
500～1000V |
| Class I |
1000～2000V |
| Class II |
2000～4000V |
| Class III |
4000～8000V |
| none |
＞ 8000V |
For devices with too strict anti-static requirements, that is, the electrostatic threshold voltage is below 100V, it is generally recommended not to use them. In special cases, it is necessary to notify the relevant departments of ZTE to take special anti-static measures.
The following table comes from Appendix 1 of "Q/ZX07.219-2005 Component Application Process Technical Requirements", which is an informative appendix for reference and not as a specification. For details, please refer to the description in the component manual.
| device type |
Electrostatic sensitivity (unit: V) |
Levels and Electrostatic Sensitivity Ranges |
| MOSFET |
100～200 |
Level 1 |
| JFET |
140～1000 |
Level 1 |
| CaAsFET |
100～300 |
Level 1 |
| CMOS |
250～2000 |
Level 1 |
| HMOS |
50～500 |
Level 1 |
| E/D MOS |
200～1000 |
Level 1 |
| VMOS |
30～1800 |
Level 1 |
| PROM |
100 |
Level 1 |
| EP-ROM |
100～500 |
Level 1 |
| SCHOTTKY DIODES |
300～2500 |
Level 1/Level 2* |
| SAW |
150～500 |
Level 1 |
| OPAMP |
190～2500 |
Level 1/Level 2* |
| N-MOS |
60～500 |
Level 1 |
| ECL circuit |
300～2500 |
Level 1/Level 2* |
| SCL (Silicon Controlled Silicon) |
680～1000 |
Level 1 |
| ECL |
500～2000 |
Level 1 |
| S-TTL |
300～2500 |
Level 1/Level 2* |
| DTL |
380～7000 |
Level 1/Level 2/Level 3* |
| Quartz and piezoelectric crystals |
＜10000 |
Level 3 |
| Note: * is a variety of possibilities, and the specific electrostatic sensitivity level should be given by the manufacturer. |
||
Placement of optical positioning points (MARK points) (from the reference " Q/ZX 04.104.2-2002 Circuit Schematic Design Specifications - Design Requirements Based on CADENCE Platform ".)
In order to be able to output the coordinates of the optical positioning point in the PCB file, the placement machine should put an appropriate amount of mark (optical positioning point) symbols on the last page of the schematic diagram according to the number of packaged devices such as BGA and TQFP.
The estimate of the number of mark symbols is as follows:
Number of marks = K + 2* ( number of QFPs with center-to-center distance of pins ≤ 0.5 mm ( 20 mil ) + number of BGA devices with center-to-center distance ≤ 0.8 mm (31 mil ) )
Among them: When mounting devices on one side, K is 3;
When mounting devices on both sides, K is 6
Try to use mount devices, double-sided reflow process. Try not to use plug-in devices.
The use of surface-mounted devices for production can increase the automation of single-board production and improve production efficiency.
The packaging of plug-in components is generally inconsistent with the size of PCB soldering holes. For example, the common discrete plug-in resistors and diodes are all taped, and the two pins are on the same horizontal line . On the circuit board, the pins must be bent (vertical or horizontal), so it is very straightforward to get its production process:
Component Forming - Insert - Wave Soldering - Inspection or Component Forming - Manual Soldering - Inspection
As for the SMD material, because the incoming material is consistent with the PCB pad package, it can be directly mounted and welded. The production process is as follows:
SMD - reflow soldering - inspection or manual soldering - inspection
From the above production process, it can be seen that the welding of discrete plug-in components requires one more molding process than that of SMD components, which increases the production process and single-board production cycle (that is, increases the cost of manpower, material resources, and financial resources);
In addition, because discrete components currently have different standards for each component manufacturer , even if the materials under the same code may be made by some manufacturers, the pins of components made by some manufacturers are long or thick, and some pins are short or thin. The packaging volume is large, and some packaging volumes are small, which brings more troubles to material selection and production process.
If a small amount of plug-in components are used, this part of the board needs to be manually soldered. If there are many plug-in devices, the efficiency of manual welding is low. When there are many plug-in devices, the wave soldering process will be used. The wave soldering process puts forward requirements for the packaging and placement of components on the B side of the board. For example, devices with exclusion, pins out around, BGA packaging, and small pin spacing must not be placed, and the placement of the devices must be consistent.
The following are the advantages and disadvantages of reflow plus peak and double-sided reflow, for your reference.
Taking a single board with SMD on both sides and discrete plug-in components on the A side as an example, its production process is as follows:
Reflow plus crest: A- side patch - reflow soldering - B -side dispensing - reflow curing - plug-in - wave - inspection
Double-sided reflow: B -side SMD - reflow soldering - A -side SMT - reflow soldering - manual soldering of discrete plug-in components - inspection
Advantages of reflow plus peak:
- The welding work can be completed at one time for a single board with many discrete plug-in components, and the efficiency is high;
shortcoming:
- Part of the devices on the board are subjected to thermal shock three times, which has a great impact on the performance and life of the devices, especially the IC on the A side ;
- The PPM value of unqualified wave soldering joints is much higher than the PPM value of reflow soldering, and there are many solder joint problems after wave soldering ;
- If there are not many plug-in components, a plug-in process is added, which increases the production process and single-board production cycle;
- The glue on the B side uses auxiliary material glue to realize the mechanical connection between the device and the PCB board, which increases the manufacturing cost.
Advantages of double-sided reflow soldering:
- Because the B side is produced first, the IC on the A side is only subjected to one thermal shock, which reduces the chance of damage to the device performance and life;
- The PPM value of unqualified reflow soldering joints is low, and the soldering pass rate is high;
- There is no plug-in process, which improves production efficiency for PCBA manufacturing with fewer solder joints , and indirectly shortens the contract delivery cycle;
- The cost of auxiliary materials is low and no additional cost will be added.
shortcoming:
- For PCBA manufacturing with many discrete plug-in components , the efficiency of manual soldering is lower than that of one-time wave soldering, which is likely to cause operator fatigue.
It can be seen from the above comparison that using SMD components and not using plug-ins as much as possible will improve production efficiency and reliability. Our department recommends this design.
Unless there are special requirements for signal integrity, devices such as series resistors should not be placed on the backplane; press-fit connectors should be used as much as possible on the backplane, and soldering connectors should be avoided.
During the processing of a large number of crimping components, it is easy to deform the veneer and cause damage to the components. And if the crimping die is pressed against the device during processing, it may cause damage to the device. Therefore, unless there are special requirements such as signal integrity, devices such as series resistance should not be placed on the backplane.
The thickness of the backplane is very thick and it is inconvenient to process. Therefore, the plug-in and surface mount connectors on the backplane often need to be soldered manually. In order to improve efficiency, the backplane should try to use crimp connectors instead of soldering connectors.
Moisture Sensitive Devices
Humidity-sensitive devices must be paid attention to during production, and pay attention to follow the corresponding specifications during storage and production.
| Moisture Sensitivity Level |
Storage conditions after unpacking |
Storage period after unpacking |
| 1 |
≤30℃/85%RH |
unlimited |
| 2 |
≤30℃/60%RH |
one year |
| 2a |
≤30℃/60%RH |
4 weeks |
| 3 |
≤30℃/60%RH |
168 hours |
| 4 |
≤30℃/60%RH |
72 hours |
| 5 |
≤30℃/60%RH |
48 hours |
| 5a |
≤30℃/60%RH |
24 hours |
| 6 |
≤30℃/60%RH |
Tab time (6 hours) |
潮敏器件应该保存在干燥箱中或者密封袋内。开包后应在规定时间内焊接完成。如果拆包时间超过规定时间，在生产之前，应对潮敏器件进行干燥处理。否则在焊接过程中温度迅速上升，封装中吸收的水分迅速气化膨胀，就会导致器件内部裂纹、剥离等“爆米花”效应，导致器件损坏。
有铅工艺和无铅工艺
2003年2月13日，欧盟发布了 WEEE《关于报废电子电气设备指令》(2002/96/EC) 、RoHS《关于在电子电气设备中限制使用某些有害物质指令》（2002/95/EC）两项指令。在两项指令中，限制铅和一些有害化学物质的使用。
至本文撰写时，我司目前已经开始无铅化生产的研究。对于高锡无铅焊料，存在低温相变、晶须生长等问题。这些问题因为专业不同，对于硬件开发人员影响并不是很大。而对于生产来说，Sn-Ag-Cu焊料的熔点为217度，较Sn-Pb焊料的183度高34度，对器件提出了更高的要求。所以，一般不能够使用无铅焊料焊接有铅元器件。
实际上现在很多采用有铅、无铅器件，用有铅焊膏混合使用的情况和试验也在进行。对于无铅的BGA和CSP封装的器件，不得使用有铅焊料进行焊接。即如果采用无铅的BGA、CSP封装的器件，则必须采用相应的焊料，这是其他器件不能采用有铅工艺器件以保证生产中的可靠性。
我们不推荐一起混合使用有铅和无铅器件