Doing embedded system development, often have to touch the hardware. To do embedded development, you must have a certain understanding of digital circuits and analog circuits. This will allow for in-depth research. Below we briefly introduce some hardware-related concepts in embedded development.
Bus (Bus)
There must be a processor chip in an embedded system. In addition, there are other chips as peripheral devices (hereinafter referred to as peripherals), and these chips cooperate with the processor to realize the functions of the product. Complex products are often made up of large numbers of chips. Then it is inevitable that we need to connect all peripherals to the processor. The simplest thing is to connect all peripherals to the processor using independent (note that they are independent) signal lines. The advantage of this is easy to understand. But here's the problem: it doesn't work.
Because the processor chip needs to lead out too many wires, it is not practical from the perspective of chip production and product production. In addition, the processor (here we assume that the processor is single-core, not multi-core) processing transactions are microscopically serial, that is to say, if you want to read and write to the peripheral at a certain time, it is only possible. It is performed on one of a large number of peripherals, that is, multiple peripherals cannot be accessed by the processor at the same time on a microscopic level.
It should be noted that the concept of micro is proposed here to distinguish it from macro. From a macro perspective, a processor can have multiple tasks running at the same time, but these tasks run one by one on a micro level (the "one by one" will be described later with serial), multitasking Serial operation is implemented by the operating system playing an important role.
Back to our topic, since it is not feasible to connect each peripheral to the processor with a separate signal line, and the processor will only access one peripheral at a time, can we use a shared signal line? What about connecting all the chips together? That's where the bus concept comes from. In layman's terms, if there are ten families around us, in order to allow every two of these ten families to communicate with each other, we do not need to build a separate (note that it is a separate) road for every two families (if so, 45 roads to build), but a big road can be built, and then every home is connected to the big road.
For the bus, we often say that the bus is the processor, and other peripherals are linked to the bus. There is a problem, we can only access one peripheral hanging on the bus at a time, so how to distinguish these peripherals? Like our way, we need to distinguish each family by address, on the bus, also distinguished by address.
In this way, buses are divided into two categories according to their functions. One is the address bus, the data on this bus will only "flow" from the processor to the peripheral, and it is unidirectional. The other type is the data bus, which is used to transfer data from the processor to the peripheral (write operations from the processor's point of view) or from the peripheral to the processor (from the processor's point of view) is a read operation), obviously, the data bus is bidirectional. That is to say, in our embedded system, both the address bus and the data bus connect all the chips that need to communicate with the processor.
The bus has a width, just as our road is divided into "three lanes" or "four lanes", when we say a 32-bit processor, we mean that its data bus width is 32 bits, that is, "there are 32 vehicles that can run at the same time." "Obviously, the wider the width, the faster our processors are, because we can access data faster from peripheral chips, which is why our computers are moving to 64-bit. Similarly, the address bus has a width, and its maximum width is 32 bits for a 32-bit processor.
With the concept of bus, the next question is, even if each peripheral has an address, where is this address recorded? Is it on the peripheral chip? If so, then there is a The problem is that the addresses of each type of peripheral must not overlap, and when two identical chips are required in a product, the addresses of the two chips cannot be distinguished. It seems that there is a problem with this operation. Also, if this were the case each peripheral would also have to be fully connected to the (say, 32) data bus and listen to the data lines to see if the processor is "calling" itself, which is complicated.
In addition, the address may also be used up due to the increase in the number of peripherals. In general, the address cannot be stored in the peripheral chip. How to let the peripheral know that it is replaced by the processor and needs to be read and written? The answer is the chip select (CS, chip select) signal of the chip. Or another number of enable (ENable) signal.
Chip Select (CS or EN)
For the peripheral chip, the chip select signal is a (also a) notification signal, telling the chip "Hey, please open the door, I want to put something in, or take something to go", the thing here can only be data , it can't be corn on the cob or something. Then there is the question, where does this signal source come from? Obviously, only from the processor. Is that also like a bus, where each chip shares a wire connected together?
If so, it is possible that all the chips of the processor "open the door" open the "door". If the processor writes the data, it is possible that all chips are written with the same data. When fetching data, each peripheral chip "throws" data outward, which will definitely cause a data bus conflict, because some chips "throw" 1 to the bus, while others "throw" 0. In this case The processor must go "crazy" because it doesn't know if it should get a 1 or a 0.
In this case, it is obviously not possible to connect all the chip select signals together, only the chip select signals of each chip are independent. The address bus was mentioned earlier. Do we use an address line to connect a peripheral chip? Or use other methods. If an address line is used to connect a peripheral chip, it may only be possible to connect up to 32 chips, which is obviously not possible.
In fact, in reality, a 32-bit number is used to represent the address of a peripheral chip. For example, 1 can represent chip A, and 6534 can represent another chip B, and so on. From this point of view, we can theoretically represent 2 to the 32nd power (4294967296) devices. The reason for this is that some devices occupy a large number of addresses. That being the case, there is another question, what if the 32-bit address bus is converted into a chip select signal of the chip? This requires the introduction of the concept of a decoder.
decoder)
The decoder converts a data into a signal on a signal line, such as a 3/8 decoder, which can convert a data with a bit width of 3 bits into 8 (2 to the 3rd power) completely independent signal lines, When binary 011 is written to the data side, it corresponds to the third of the 8 lines, and when binary 111 is input, it corresponds to the last of the 8 lines. With the decoder, the address lines of the processor are simplified. As long as 32 address lines are added with an external decoder, a large number of peripheral chips can be accessed. The choice of external devices, we have solved, now have to look back at the data bus.
In an embedded system, the data bus of all chips can be understood as being directly connected. The word "understandable" is used because a bus driver is added in order to increase the load capacity of the bus. In order to understand, let's take a look at the tap water in our lives. For example, in Beijing, all the water pipes may be connected together in theory, but in order to increase the water pressure, there are many small water stations to increase the water supply pressure, and It is impossible for all the tap water in Beijing to come from a single water plant.
Now that all the data buses are connected, there can be problems. When writing data to an external device, the processor first transmits the address of the target peripheral to the address bus, and the address decoder converts it into a chip select signal of a signal and sends it to the target peripheral. After the target peripheral receives this signal , to open the "door". Next, the processor will put the data to be sent to the peripheral on the data bus. Since only the target peripheral chip has opened the "gate", the data will only enter the target peripheral, and other peripherals will not receive anything. arrive. Great! The processor should have no problem writing data out, let's look at reading next. In the case of reading, since the data is transmitted from the peripheral to the processor, although we use the same method as writing to open the "gate" of the target peripheral, at this time, other peripherals are also on the data bus, and they may be in 1 may also be at 0, will it affect the processor to read the data of the target peripheral? The result is of course not, but we have to introduce another concept: high-impedance state.
High impedance state
Obviously, when the processor reads data from the target peripheral, we hope that the data bus of other chips that are not selected will not affect the data to be transmitted by the target peripheral. What should we do? In fact, when the chip has no When selected, their data buses are all high impedance. The so-called high-impedance state, we can understand that this pin is disconnected inside the peripheral chip, so it will obviously not have any effect on the processor reading data from the target peripheral. We say that when a chip is not selected or enabled, its data bus must be in a high-impedance state. The opening and closing of the "gate" was used as an example. What does the "gate" mean? It refers to the data bus of the peripheral. The function of the chip select signal is to control the connection between the data bus of the peripheral and the data bus of the processor. connected or disconnected. For more explanations about high-impedance states, please refer to the article "High-impedance states and tri-state gates" written earlier.
drive
Whoever puts the data on the bus, we say who is the driver at that moment. That is, when the processor writes data to a peripheral, it is driving the data bus, and when the processor reads data from the target peripheral, the target peripheral is driving the data bus. As for the address bus, the address bus is always driven by the processor because it is only possible to write from the processor to the target peripheral. When a chip is not selected, we say it does not drive the data bus.
Tri-state gate
Earlier we mentioned that the data bus of the peripheral chip is in a high-impedance state when it is not selected. When it is selected, its level may be high (1) or low (0). In this way, we say that the chip pins of the peripheral data bus belong to three-state gates, that is, there are three states: high-level, low-level and high-impedance state. For more explanation about tri-state gates, please refer to the article "High-impedance state and tri-state gate" written earlier.
level validity
Earlier we learned what a chip select signal is, and also talked about a tri-state gate. It should be pointed out that a chip select signal is usually not a tri-state gate, and it only has two states, that is, a high level or a low level. We also said earlier that the chip select signal is used to "open the door", and the chip select signal has high and low levels. Does high level mean "open door"? Or low level? For this question , we say that if a level represents "open door" for a chip select signal, then it is the effective level of this signal. For example, for a chip select signal, if the low level means "opening the door", then we say that the chip select signal is active low. Although, here we use the chip select signal to explain the validity of the level, but many signals have validity problems. For example, the read signals and write signals that we will talk about later have validity problems.
timing
Earlier we mentioned that when the processor wants to write data to a peripheral chip, it needs to put the address of the peripheral to be accessed on the address bus first, and then the decoder converts the data on the address bus into chip select signal, the chip select signal enables the target peripheral chip, and then the processor writes data to the data bus to complete a write operation. Obviously, the data on the address line must be kept for a period of time before the processor writes the data to the data bus, otherwise the decoder cannot make the chip select signal valid for a long time. When the data write operation is completed, the processor does not need to ensure that the address on the address bus is valid.
We can see that this series of operations have a certain strict time sequence, which is called timing. The timing describes the "procedure" of the interaction signal between the processor and the external device. Only by following this "procedure" can the normal communication between the processor and the external device be guaranteed. It's like the traffic lights on our roads, if we pedestrians and vehicles don't follow their directions, there will be accidents. Typically, timing diagrams are used to describe the signal "discipline" of communication between chips.
From the figure, we can see that ADDRESS represents the address bus, DQ represents the data bus, CE is the chip select signal, and it is active low, and its width must be guaranteed to be always valid during read operations. Learning to read timing diagrams is very helpful for embedded system development, because we inevitably have to deal with chips. In a sequence diagram, a lot of time requirement information is usually identified. When writing the startup code, it is necessary to initialize the chip select address register and read and write timing of each address space. The timing configuration is based on the time requirements of the peripheral chip, which is an important part of the chip manual. When there are multiple peripheral chips in an address space, we need to consider the time requirement of the slowest peripheral chip, otherwise some chips will not work properly.
read signal
When the processor needs to read a signal from a peripheral chip, in addition to generating a chip select signal, it also needs to tell the peripheral chip that this is a read operation, not a write operation, which is achieved by reading the signal.
write signal
I talked about the read signal earlier. I think it is not difficult to understand the write signal. This signal is used to tell the peripheral chip that this is an operation to write data to the peripheral chip.
I/O ports
Peripherals (chips) were mentioned earlier, and now is the time to categorize peripherals. In general, peripherals are divided into two categories, one is memory peripherals, and the other is non-memory peripherals, the latter is often called I/O devices, where I/O is the abbreviation of Input/Output, that is input Output. It can be seen that I/O peripherals are a very broad concept. For memory peripherals, its characteristic is that the space it occupies is a continuous piece. For example, SDRAM memory belongs to memory peripherals. If its capacity is 8M bytes, the address space occupied by it will also be 8M.
Unlike memory peripherals, I/O peripherals typically use very few addresses. For example, an I/O peripheral may have multiple control registers. These control registers are multiple I/O ports (addresses) from the perspective of the processor. Writing data to this address is writing data to the register corresponding to the peripheral. , can also be read. For example, a serial port chip may have multiple registers, one is used to query the state of the chip, one is used to set the function of the chip, the other is used to read the data received by the chip from the serial port line, and finally, there is another one used for Write data to the chip to send data to the serial line. For the registers of this serial chip, from the point of view of the processor, they are all independent I/O ports.
I/O ports have read and write problems. Some ports are read-only, some are write-only, and some are both readable and writable. The read-write performance is determined by the registers of the peripheral chip. The decision can be found in the chip's data sheet. It should be pointed out that some memory peripherals also have I/O ports for some control over them. From the name of the I/O port, for the processor, it is a general term for an interface that reads data from the outside or outputs data to the outside.
interrupt
From the hardware point of view, an interrupt is a signal line that can generate high and low levels, but understanding it needs to be from the processor's point of view. We have said that from the microscopic point of view, the work done by the processor is carried out in sequence, and its processing of the program can only be the execution of one instruction and one instruction. If there is a need to access the peripheral chip, and it is possible to issue read and write commands from the processor, since the peripheral is usually much slower than the processor, the peripheral chip needs some time to prepare the required data. In this case, if the processor has been waiting for the return data from the peripheral chip to execute subsequent instructions, it will consume precious time, which can be used for other work.
Don't forget, from a macro perspective, processors are often multitasking, and a task is a scheduling unit provided by the operating system. When a task is blocked due to waiting for data from the peripheral chip, we can switch to another task to improve processing efficiency. This has a problem. When the processor is going to process another task, if the data of the peripheral chip is good, what if the processor is told? By the way! It is through the interrupt signal. The high and low levels of the interrupt signal can be used to indicate whether there is an interrupt that requires the processor's attention to handle a specific event (eg, an event that peripheral data is ready).
From this point of view, the introduction of interrupts can greatly improve the efficiency of the processor. In order to use the interrupt on the processor, we need to initialize the interrupt controller of the processor at the beginning, such as installing the required interrupt service routine or called ISR (Interrupt Service Routine), and then open the interrupt mask bit. The following operations need to be done in the interrupt service routine:
1. Read in or write data from the peripheral. Read or write usually requires reading the peripheral's interrupt status register to decide.
2. Clear the interrupt signal of the peripheral. We know that the interrupt signal is driven by the peripheral chip. In order to tell the peripheral chip that the processor has completed the required work, the processor needs to notify the peripheral chip in a certain way. This method is to write a bit of data in the register of the peripheral chip. For example, it may be written to 1 to clear the interrupt, or it may be written to 0 to clear the interrupt, which is usually available in the peripheral data sheet. found. When the peripheral receives the clear interrupt request from the processor, it will drive the interrupt line to make it invalid. For example, the interrupt line of a peripheral is when it is low to indicate that there is an interrupt, and changing it from low to high is driven to inactive.
3. Clear the processor's interrupt signal flag. The processor also often saves whether the external interrupt signal has occurred. When we have finished processing the interrupt of the peripheral chip, we also need to clear the flag on the processor to prepare for the next interrupt. It should be noted that the interrupt to clear the peripheral must occur before the processor interrupt flag!
There is also an issue with how interrupts are triggered. There are two trigger modes, one is level trigger and the other is edge trigger. Level-triggered means that the level of the level indicates whether the peripheral has an interrupt, while edge-triggered can be represented by the rise or fall of the level on the interrupt line. Obviously, there are two edge-triggered methods. One is when the interrupt line changes from a low level to a high level, which we call a rising edge trigger, and the other is when the interrupt line changes from a high level to a low level, which we call a falling edge trigger. In general, the triggering methods of interrupts are level-triggered, rising-edge-triggered and falling-edge-triggered. An important step in interrupt setting in processing in level-triggered mode.
multimeter
A multimeter is usually used to check the level of the level, the size of the resistance, etc. It is one of the commonly used and indispensable tools. In the development of embedded systems, we commonly use digital multimeters.
Level
In digital circuits, it is divided into high level and low level, which are represented by 1 and 0 respectively. The pins of a digital circuit always have a level, either high or low, or 1 to 0 (in fact, there is another state).
oscilloscope
In embedded system development, we inevitably have to deal with peripheral chips. When debugging a driver, in addition to fully understanding the data sheet of the chip, and in the process of software level, we also need to see whether the signal level we expect occurs on the chip. For example, when we write a driver, we need to operate the peripheral chip by writing the I/O port. When writing the corresponding I/O port, we know that the chip select signal of the corresponding chip should be valid. Sometimes, we need to verify Does it happen as expected, which requires the use of an oscilloscope.
A general oscilloscope can observe the signal states of two signal lines at the same time. Oscilloscopes all provide certain functions, such as setting the way of signal capture and so on. A very important parameter of an oscilloscope is its acquisition frequency. According to the Nyquist acquisition theorem, if we want to use an oscilloscope to view a signal with a frequency of 100M Hz, then its sampling frequency must be at least twice that, that is, 200M Hz. Some people may ask: Why don't you use a multimeter to see it? Because the multimeter's acquisition frequency is very low, it is impossible to collect rapid signal changes.
logic analyzer
Simply put, a logic analyzer is an oscilloscope with many signal channels. With a logic analyzer, we can see the data on the address bus and data bus. Logic analyzers all provide certain programming capabilities for programming when to start collecting data on the bus.