Table of contents
Number System and Coding
Representation of characters and strings
ASCII code
The ASCII code character system has 128 elements, so binary encoding requires 7 bits, plus an even parity code, a total of eight bits, exactly one byte. It is stipulated that the highest bit of the 8 bits is 0, and the remaining 7 bits can give 128 codes.
Among the 128 codes, there are 95 displayable characters, and the number range is 32-126. There are 33 control characters, and the number range is 0-31 and 127.
Chinese character encoding
Input code: digital code, pinyin code, font code, etc.
Chinese character internal code: internal code for storing, exchanging and retrieving Chinese character information, composed of two bytes, the high bit of each byte is 1
Output code: font code
Representation of fixed-point and floating-point numbers
Fixed-point numbers, that is, the position of the decimal point of all data is fixed, and can be divided into fixed-point decimals and fixed-point integers.
In order to facilitate the processing of sign bits and value bits when performing operations on data, the computer codes the sign bits and value bits together to represent data. These codes are called machine codes.
fixed-point representation
The machine code representation part is relatively simple and will not be described in detail. You can refer to https://blog.csdn.net/btufdycxyffd/article/details/127775989?spm=1001.2014.3001.5502
Original code notation
Inverse code notation
Complementary notation
Original code change The way to complement it:
- The sign bit of the original code is 1 unchanged, and each binary digit of the integer is negated to obtain the inverse code
- The sign bit of the inverse code is 1 and remains unchanged, and the lowest bit of the inverse code value is added with 1 to obtain the complement code
Frameshift notation Frameshift
is usually used to represent exponents of floating-point numbers.
The mantissa of the code shift and the complement code are the same, but the sign bit is opposite
Floating point representation method
The floating-point number means that the position of the decimal point of the data can float within a certain range.
Current computers use the format in the IEEE754 standard to represent floating-point numbers. The standard format for specifying 32-bit short floating-point numbers and 64-bit long floating-point numbers is
S represents the sign bit, E is the order code, M is the mantissa, the mantissa uses the original code, and the exponent uses the code shift (to facilitate order comparison and comparison).
When the value of the mantissa is not 0, the most significant bit of the mantissa field is 1. The form is: 1.M, the highest digit 1 is regarded as hidden on the left side of the decimal point to improve the precision of data representation.
The order code adopts the frame shifting method (adding a fixed offset value), and when changing the true value of the index e into the order code E, add a fixed offset value of 127, that is, E= e+127.
Machine zero: When the mantissa of a floating point is 0, regardless of the value of the exponent; or when the value of the exponent is smaller than the minimum value of the exponent, regardless of the value of the mantissa, it is regarded as machine zero.
The base R=2, the base is fixed, and it is expressed in an implicit way.
Normalization :
Original code: The highest digit of the mantissa must be a valid value.
Two's complement: the most significant bit of the mantissa must be the opposite of the sign bit of the mantissa.
Why normalize?
Answer: If there is no clear regulation on the representation of floating-point numbers, the representation of the same floating-point number is not unique.
The true value of the normalized 32-bit floating-point number x is:
The true value of the normalized 64-bit floating-point number x is:
Representation range of floating point numbers
Example: If the binary storage format of the floating-point number x is (43AC0000)16, find the decimal value of its 32-bit floating-point number.
Solution: After expanding the hexadecimal number, the format of the binary number can be obtained:
exponent e=order code-127=10000111-01111111=00001000=(8)10
Mantissa 1.M=1.010 1100 0000 0000 0000= 1.01011
So the truth value:
Operations with fixed-point and floating-point numbers
Operations on fixed-point numbers
two's complement addition
[x+y] complement=[x] complement+[y] complement (mod 2n+1)
two's complement subtraction
Mantra: negate and add 1 to the last digit
[xy] complement = [x] complement - [y] complement = [x] complement + [-y] complement
[-y] complement = -[y] complement (mod 2n+ 1)
[-y] complement = [y] complement and negation + 2-n
overflow concept and detection method
The concept of overflow: the phenomenon that the absolute value of the word length appears in the operation
Overflow detection method: double sign bit method (distorted complement code), single sign bit method Double sign bit method
[
x] complement = 2n+2 + x ( mod 2n+2 )
Sf1 represents the correct sign, and the logical expression is V= Sf1 ⊕ Sf2
Example: x=+01100 , y=+01000 , find x+y .
fixed-point multiplication
Array multiplier: A pipelined array multiplier is used to replace the serial scheme
[x] original=xf.xn-1…x1x0 [y] original=yf.yn-1…y1y0[xy] original=(xf ⊕ yf)+ (xn-1…x1x0).(yn-1…y1y0)
The operation rules for multiplying the numbers represented by two original codes are: the sign bit of the product is obtained by the exclusive OR operation of the sign bits of the two numbers, and the value bit is obtained by two The product of multiplying integers is obtained.
Array multiplier without sign bit Array multiplier
with sign bit
Complementary circuit:
When E=0, the input and output are equal, and when E=1, scan from the rightmost end of the number to the left until the first 1 , this bit and the bits on the right remain unchanged, and the values on the left are reversed bit by bit.
Direct original code multiplication : when inputting the original code and performing multiplication, there is no need to seek complementation before calculation and complement after calculation. The product is immediately available.
Example: Set x=+15, y=-13, use the original code array multiplier with a complement
to find the product x y=? Complement to get the absolute value of each number. After calculation, the complement is obtained to obtain the complement of the product.
Example: Set x=-15, y=-13, use a complement array multiplier with a complementer to find the product x·y=? and verify it by multiplying decimal numbers.
fixed point division
Assuming n-bit fixed-point decimals (fixed-point integers are also applicable) dividend x, [x] original = xf
. , [q] The original = (xf⊕yf) + (0.xn-1...x1x0/0.yn-1...y1y0)
quotient symbol operation qf=xf⊕yf is the same as the original code multiplication, and the sum is obtained by modulo 2 .
Restoration method of original code
In manual division, people can compare the dividend (remainder) and the size of the divisor to determine the quotient 1 (enough subtraction) or quotient 0 (not enough subtraction). In machine division, a positive remainder means sufficient subtraction, and a negative remainder means insufficient subtraction. When the subtraction is not enough, the original remainder must be restored to continue the downward operation.
This method is called the recovery remainder method, and the control is more complicated.
The original code does not restore the remainder method (addition and subtraction alternate method)
If the remainder is positive, the quotient is 1, and the next divisor is shifted to the right for subtraction; if
the remainder is negative, the quotient is 0, and the next divisor is shifted to the right for addition.
The number of calculation steps is fixed, and the control is simple and regular.
Example: x＝0.101001, y＝0.111, find x÷y.
Array divider that does not restore remainder
Operations on floating point numbers
Addition and subtraction of floating-point numbers
There are two floating-point numbers x and y, which are respectively
x=2E^x·Mx y=2E^y·My
where Ex and Ey are the order codes of numbers x and y respectively, Mx and My is the mantissa of the numbers x and y.
The operation rules for addition and subtraction of two floating-point numbers are: x±y=(Mx2 (Ex-Ey)±My)2 Ey
Operation steps
- 0 operand check; when encountering 0, bypass processing can be done
- Compare the order codes and complete the order alignment (small order to large order alignment);
The rule is that the number with the smaller order code is aligned with the number with the larger order code; the small order is with the large order;
△E =[Ex]complement-[Ey]complement
- If the step difference △E=0, it means that the two order codes are equal, that is Ex=Ey;
- If the step difference △E>0, it means Ex>Ey;
- If the step difference △E<0, it means Ex<Ey.
- When Ex≠Ey, Ex or Ey should be changed by moving the mantissa to make them equal.
- Mantissa addition and subtraction operations;
- Normalization of results ;
I don't quite understand this part, please refer to https://blog.csdn.net/weixin_43715360/article/details/120256108 for details
If the sign bit of the mantissa summation result is represented by a double sign bit, the result is 10.&&&&& or 01.&&&&&, that is, the double sign bits are not equal, which is called overflow in fixed-point addition and subtraction operations. In the floating-point operation, it indicates that the absolute value of the operation result is greater than 1, which destroys the normalization. At this time, the normalization process needs to be shifted to the right. When the highest bit of the numerical value is invalid ( note that the original code and complement code are different ), the highest bit of the numerical value is valid by shifting the mantissa to the left.
- Right rule processing: when the mantissa operation overflows, shift right by 1 bit, and add 1 to the exponent code.
- Left rule processing: when the mantissa operation does not overflow, and the mantissa is not 1.M (this part is not very clear, there are also examples, I don’t know if it is right, write it down first), then the mantissa is shifted to the left by 1, and the order code is reduced 1.
- rounding processing;
- Nearest rounding (0 rounding 1): similar to "rounding", the highest bit discarded is 1
- Rounding from 1 to 0: truncation
- Rounding towards +∞: If the extra digits of positive numbers are not all "0", carry 1; for negative numbers, truncate
- Rounding towards -∞: the extra digits of negative numbers are not all "0", carry 1; positive numbers, truncate
- Overflow handling.
The exponent code overflow is generally considered as +∞ and -∞. If the exponent code underflows, the value is 0.
Example: Let x=2^010×0.11011011, y=-2^100×0.10101100, find x+y.
Solution: Both the order code and the mantissa are represented by complement code
[x] floating complement = 00010, 0.11011011; [y] floating complement = 00100, 1.01010100
① 0 operand check (not 0): increase the operation speed
② Alignment: addition and subtraction can only be done after the order codes are aligned
The step difference of this question △E = [Ex] complement - [Ey] complement = 00010-00100=11110=-2D,
that is, the step difference is -2, Mx is shifted to the right by two places, and Ex is added by 2.
[x] Floating compensation=00100, 0.00110110(11)
③ Mantissa addition or subtraction
④ Result normalization
If the mantissa is not 1.M, the left normalization process becomes 1.000101 01(10) , and the order code 00100 minus 1 becomes 00011
⑤ The rounding process
adopts the nearest rounding (0 rounding 1 into) method to get 1.000101 10 .
⑥ Judgment and processing of overflow
The sign bit of the exponent code is 00, no overflow. The final result is x+y = 2^011×(-0.11101010)
Multiplication and division of floating point numbers
The operation steps are the same as above
The composition of the calculator
The arithmetic unit is composed of an arithmetic logic unit (ALU) (core) , an accumulator, a status register, a general-purpose register group, and the like.
The main function of the calculator is to complete the arithmetic and logic operations on the data , which is undertaken by an internal arithmetic and logic operation unit (ALU). It not only gives the operation results, but also gives some of the results Features, such as overflow or not, whether there is a carry output, whether the result is zero or negative, etc. These result characteristic information are usually stored in several specific flip-flops.
During the execution of an instruction, the ALU must be provided with control signals as to what operation it performs.
The function of the register : temporarily store the data and intermediate results that will be involved in the operation. These registers can be directly accessed by the assembly programmer. They are commonly called general-purpose registers to distinguish them from those special registers that are set inside the computer and cannot be accessed by the assembly programmer.
Arithmetic Logic Unit (ALU)
ALU has 2 units, one is arithmetic unit and one is logic unit .
Arithmetic Unit: Responsible for numerical operations in the computer, such as addition and subtraction.
Logic unit: Responsible for logical operations in the computer, such as AND, OR, NOT, XOR, etc.
In addition, the ALU also has auxiliary functions: shifting, complementing, etc.
arithmetic unit
One-bit full adder: the most basic addition unit, input two-bit addend and low-order carry, output sum and high-order carry
Serial adder: simple connection of one-bit full adder, serial carry
Parallel adder: use lookahead Carry improves the operation speed of the adder
74181ALU logic circuit diagram
Realization of arithmetic and logic operations (74181ALU)
① When M=L=0, there is no effect on the carry signal, and arithmetic operations are performed
② When M=H=1, the carry gate is blocked and logic is performed operation
logic unit
Logical units perform logical operations, such as AND, OR, and NOT operations, and they can also perform simple numerical tests, such as whether a number is negative.
internal bus
The data transmission of each part inside the machine is frequent. In order to reduce the internal data transmission lines and facilitate the control, the data transmission paths between the registers can be merged to form a bus structure.
Bus Classification:
Location
- Internal bus (within CPU)
- External bus (system bus)
logical structure
- unidirectional transfer bus
- bidirectional transfer bus
The basic structure of the calculator
A calculator with a single-bus structure
A calculator with a dual-bus structure A
calculator with a three-bus structure
