To manually generate two sinusoidal signals of different frequencies, then two waveform signals superposed high and low-pass filtering process, beginning Mr. into two sinusoidal signals, the mixed signal is generated by the multiplier by modelsim simulation to verify the design.
This case is designed with Block Design method (you can also choose to write .v file form design).
Signal source generates
The simple case of two sinusoidal signals generated by DDS IP core, in order to facilitate observation of the back, respectively, to generate a sine signal and a 4M 5M here.
Double-click to open DDS IP core into the set, to set parameters
The case related settings are as follows:
Is the default setting, the following is an explanation of each parameter
After completion of setting the parameters, you can view the information in the Output Frequencies in the frequency.
Similarly, the view parameter settings in the Summary options
Wherein the fixed number of bits is eight sinusoidal amplitude is maximum d'126 (8'b0111_1111), the most significant bit is the sign bit.
mixing
Call a multiplier, the two sinusoidal signal mixing, the observed signal after mixing.
Connection
After the IP module selection is complete, it can be wired, first select the DDS IP of aclk pins
M_ASIS_DATA then the DDS output pins are connected to the two mult_gen IP cores A and B, after the right-click pin P, select pin to create port automatically generated output.
Right-click the blank space, choose valid design, the following window appears, indicating that the connection is not wrong.
After the connection is completed, the file generating core block top block.
Select create a HDL wapper, generates a top-level document.
Generating block design
This step can not lose the right simulation
Write simulation files for simulation
Add the following two output waveforms sinusoidal
It should set the waveform display, select wavefrom style and radix - signal decimal, so as to correct the waveform shown above.
