ARM exception handling (3): Bus faults, Memory management faults, Usage faults, Hard faults detailed explanation

I introduced ARM exception handling (1) before: exception type, priority grouping and exception vector table . There are many exception types in it, and several exceptions are very useful in error handling:

1 Bus Fault

Raised when an error response is received during transmission on the AHB interface Bus fault. It can happen in several stages:

• The instruction prefetch stage, often called theprefetch abort
• data read/write phase, commonly referred to asdata abort

In Cortex-M3, the following situations will also occur Bus fault:

• The stack is PUSHed at the beginning of interrupt handling, calledstacking error
• The stack is popped at the end of the interrupt handling, calledunstacking error
• When the processor begins the interrupt handling sequence, the interrupt vector address ( vector fetch) is read ( Hard faulta special case of

Features:

If no Bus faulthandler is enabled or if a bus error occurs in another Bus faultexception handler than a higher-priority exception, Hard faultthe interrupt handler function will be bus faultexecuted instead. If Hard faultanother is generated in the middle of processing Bus fault, the core will go into a locked state.

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Common causes of AHB error responses

• An attempt was made to access an invalid memory region
• The device is not ready for transmission (such as accessing a peripheral without initializing it)
• The word transfer size not supported by the target device (for example, a peripheral register only supports word access, while the program accesses byte by byte)
• Device does not accept transfers (e.g. some peripherals can only be programmed at a privileged access level)

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1. How to enable Bus faultthe handler? Set the bit
in the NVIC . Before that, you need to ensure that the starting address of the handler is set in the interrupt vector table.System Handler Control and State registerBUSFAULTENABus fault

2. Bus faultWhen entering the processing program, how to judge what went wrong?
    NVIC has many error status registers ( Fault Statuc registers), one of which is the bus error status register ( Bus Fault Status register,BFSR), from which you can know whether the error is caused by data/instruction access or interrupt stack and other reasons.
    If you want to locate more accurately Bus fault, you can locate the wrong instruction through the stack program counter, and if the bit BFSRin it is 1, you can also determine the resulting memory location by reading the bus error address register ( ).BFARVALIDBus Fault Address Register,BFARBus fault

• In some cases, the information in these registers is inaccurate, because when the processor receives the error, many other instructions may have been executed. For example, for writing data to a buffer, if an error may occur after multiple clock cycles Bus fault, this is called unprecise bus fault ; while for reading memory, the next instruction cannot be executed before the read is complete, so at this time An error is generated immediately Bus fault, which is called precise bus fault.

Bus Fault Status RegisterLocated at memory address 0xE000ED29, its fields are as follows:

Bits	Name	Type	Reset Value	Description
7	BFARVALS	-	0	Indicates whether BFAR is valid
6:5	-	-	-	-
4	STKERR	R/Wc	0	Stacking error
3	INSTANTANEOUS	R/Wc	0	Unstacking error
2	IMPRECISERR	R/Wc	0	Imprecise data access violation
1	PRECISERR	R/Wc	0	Precise data access violation
0	BUSERR	R/Wc	0	Instruction access violation

• To access this register, you can access 0xE000ED29 by byte, or you can access 0xE000ED28 by word to get the second byte
• Writing a 1 to an error indication bit will clear the state of the bit

2 Memory Management Fault

Memory management errors can be caused by illegal access to the MPU (Memory Protection Unit Memory Protection Unit) or some illegal access such as executing code in some non-executable memory area. Common MPU errors are as follows:

• Access to undefined memory region in MPU
• Write data to the read-only area
• Access memory that can only be accessed in privileged mode in user state

The memory management error handling function Bus faulthas the same features as the ones , and will not be repeated here. To enable the handler for memory management errors, a bit in the NVIC needs to be System Handler Control and State registerset MEMFAULTENA.

The NVIC contains a memory management error status register ( Memory Management Fault Status Register,MFSR) to indicate the cause of a memory management failure. DACCVIOLIf the data access illegal ( ) bit or the instruction access violation ( bit) in the status register IACCVIOLis 1, the wrong code can be located by the stack program counter. MFSRIf the bit in is set , the memory address location that caused the error MMARVALIDcan also be determined from the memory management address register ( ) in the NVIC .Memory Management Address Register,MMAR

MFSRThe register is shown in the table below, its address is 0xE000ED28, and the fields are as follows:

Bits	Name	Type	Reset Value	Description
7	MMARVALS	-	0	Indicates whether MMAR is valid
6:5	-	-	-	-
4	MSTKERR	R/Wc	0	Stacking error
3	MUNSTKERR	R/Wc	0	Unstacking error
2	-	-	-	-
1	DACCVIOL	R/Wc	0	Data access violation
0	IACVIOL	R/Wc	0	Instruction access violation

• Access to this register can be accessed by byte or by word 0xE000ED28
• For others FSRs, writing a 1 to the error status bit will clear the error status

3 Uage faults

Usage faultsIt may be caused by the following situations:

• undefined instruction
• Coprocessor instructions (Cortex-M3 does not support coprocessors)
• Try switching to ARM state(you can use this mechanism to test whether the processor supports it ARM state; Cortex-M3 does not support it, and a usage error will occur if you switch)
• invalid interrupt return ( LRregister contains invalid/incorrect value)
• loadUsing multiple / storedirectives for unaligned memory

By setting some bits of NVIC, the following two types can also be generated Usage fault:

• division by 0
• access any unaligned memory

Usage faultsHandlers Bus faulthave the same characteristics as , and to enable Usage faultshandlers, you need to set bits in the System Handler Control and State registerNVIC USGFAULTENA.

The NVIC contains a usage error status register ( Usage Fault Status Register,UFSR) to indicate the cause of a usage error. Inside the handler, the program counter value of the stack can also be used to locate the program code that caused the error.

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One of the causes Usage fault: One of the most common reasons for switching toARM state
Usage fault is to inadvertently switch the processor to ARM state, which occurs after the user loads an address with an LSB of 0 PC. For example, we want to use BXthe or BLXinstruction to jump to an LSB that does not have an address set, and the LSB of the vector in the exception vector table is 0; or we want the POPPC value already on the stack, and the LSB is 0. In these cases, Usage faultwill be generated, UFSRthe register INVSTATEwill be set.

• The lowest bit LSB is 1 to indicate the use ofThumb state

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UFSRThe register is shown in the table below, its address is 0xE000ED2A, and the fields are as follows:

Bits	Name	Type	Reset Value	Description
9	DIVBYZERO	R/Wc	0	Indicates whether it is an error caused by dividing by 0 (need to be set DIV_0_TRP)
8	UNALIGNED	R/Wc	0	Indicates whether the error is caused by byte misalignment
7:4	-	-	-	-
3	NOCP	R/Wc	0	Attempt to execute a coprocessor instruction
2	INVPC	R/Wc	0	EXC_RETURNAn exception for an incorrect return value in an attempt to execute
1	INVESTED	R/Wc	0	Attempt to switch to an invalid state (eg ARM state)
0	UNDEFINSTR	R/Wc	0	attempt to execute an undefined instruction

• To access this register, you can access 0xE000ED2A by byte, or you can access 0xE000ED28 by word to get its highest byte
• For others FSRs, writing a 1 to an error status bit will clear the error status of that bit

4 Hard Faults

If Usage faults, Bus faultsand Memory management faultshas no corresponding error handler, one will be generated Hard fault. vector fetchIn addition, it can also be caused by reading the vector table ( ) during the execution of the exception handler Bus fault. There is a hardware error status register ( HFSR, Hard Fault Status Register) in the NVIC that can be used to determine if the error is vector fetchcaused by . If not, then Hard faultyour error handler needs to check something else FSRsto determine Hard faultthe cause.

HFSRThe register is the same as others FSRs, and the error status can be cleared by writing 1. The address of this register is 0xE000ED2C, and its fields are as follows:

Bits	Name	Type	Reset Value	Description
31	DIVBYZERO	R/Wc	0	Indicates whether the error was caused by a debug event
30	FORCED	R/Wc	0	Indicates whether the error was generated by Usage faults, Bus faultsandMemory management faults
29:2	-	-	-	-
1	VECTBL	R/Wc	0	indicates that the error is vector fetchcaused by
-	-	-	-	-