When learning Python, the author has a sentence that has a great influence on me. The author wants us to pay attention to some industry conventions when we learn to write programs. In the eyes of the layman, your writing format has already exposed your level. The same is true for learning verilog. A good verilog code, on the premise of completing the design requirements, needs to be well organized and have corresponding annotations, which should be friendly to non-authors. Because the digital IC design is still in its infancy, what I wrote in the early stage is basically based on the collection of data, adding a part of personal understanding, hoping to precipitate my own unique insights through my own continuous learning.
Regarding the Verilog writing specification, the information on the Internet is relatively scattered, and I think the better one is the 2001 version of Huawei's writing specification. Hereinafter referred to as the specification (https://wenku.baidu.com/view/bbad6339fe00bed5b9f3f90f76c66137ee064fc8.html) Baidu Wenku
I'll add a few additions to the sub-spec:
1. Active low signal, add '_n' after the signal.
2. The module name is lowercase.
3. The module instantiation name is represented by U_xx_x (multiple instantiations use the sequence number 0.1.2...).
4. Use descending sort to define the vector significand order, with the least significant bit being 0.
5. Use lowercase letters to define reg, wire and input/output/inout.
6. Use uppercase letters to define parameters, and the parameter name should be less than 20 letters.
7. The clock signal should be prefixed with 'clk' and the reset signal should be prefixed with 'rst'.
8. Tri-state output register signals should be suffixed with '_z'.
9. VHDL reserved words and Verilog reserved words cannot be used in the code. ps: There are specific reserved words that can be searched by Baidu, which are not listed here.
10. Output signals must be registered (for top-level modules only). ps: This is mentioned in the various materials consulted.
11. Tri-state logic can be used in top-level modules, and tri-states are avoided in sub-modules.
12. There are no unconnected ports.
13. For interface signals to other modules, define port signals in the following order: input, (bidirectional), output.
14. It is recommended to use coregen to generate multiplication circuits.
15. Use name-based calls instead of sequence-based calls.
16. Do not write empty modules, that is, use a module with at least one input and one output.
17. Clock events should be expressed in the form of 'negedge<clk_name>' or 'posedge<clk_name>'.
18. Asynchronous reset, use 'if(<rst_name> == 1'b1)' for high level and 'if(<rst_name> == 1'b0)' for low level. The bit width of the judgment condition in ps:if is 1.
19. If statements cannot be nested too much.
20. It is recommended not to use the include statement.
21. It is recommended to add timescale to each module.
22. The necessary comments are given in the code.
23. Each file has a header. ps: My understanding is that comments should be applied at the beginning of each file, including the name, function, version, time, etc. of the module written.
24. Each file contains only one module.
25. The module name is consistent with the file name.
26. There is only one clock signal in the always block of synchronous sequential logic, and it acts on the same edge (such as rising edge).
27. In the module of synchronous sequential logic, it operates on the same edge of the clock signal.
28. Adopt synchronous design and avoid using asynchronous logic (except global signal reset).
29. Generally do not input the clock signal as a data signal.
30. Do not add any buffers to the clock path.
31. Don't gate clocks. ps:
32. In the top module, the clock signal must be visible.
33. Do not use a vector to define a set of clock signals.
34. Do not generate the clock signal inside the module, use the clock signal generated by the DLL/PLL.
35. It is recommended to use a single global synchronous reset circuit or a single all asynchronous reset circuit.
36. Do not add any buffers to the reset path, and do not use any gated reset signals. ps: Adding a buffer to the reset path will cause a delay from the reset signal to the trigger reset receiving port. The generation of skew may not meet the reset recovery time, resulting in the generation of metastable states. Gating can cause glitches on the reset signal, increasing the likelihood of metastability.
37. Do not use PLI functions.
38. Don't use event variables.
39. Do not use system functions.
40. It is recommended not to use tasks.
41. Does not use User Defined Units (UDP).
42. Do not use ===, ! == and other non-synthesizable operators.
ps: Supplement Verilog non-synthesizable statement.
initial (only used in testbench), events (more useful when synchronizing testbench), real time, assign and deassign (reg type cannot be synthesized, but wire type can), fork join, primitives (only gate-level primitive synthesis is supported) , table, sensitive list with both posedge and negedge (such as always@(posedge clk or negedge clk) begin end this cannot be synthesized), the same reg is driven by multiple always blocks, delay #time, such as a = #5 b , it is possible to simulate here, but #time will be automatically ignored during synthesis, which is equivalent to a = b, X or Z (unknown state and high resistance state), do not use them in conditional expressions, make sure you can comprehensive.
43. Do not use the disable statement.
44. It is recommended not to use forever, repeat, while loop statements.
45. Avoid generating latch (except CPU interface). ps: In all conditional branches in the if statement or case statement, there is a clear assignment to the variable, otherwise the latch will be synthesized.
46. The sensitive variables in the combination logic block sensitive list must be consistent with those used in the module, neither more nor less.
47. In an always statement, there is one and only one event list.
48. In the sensitive event list of the timing always block, all must be edge-triggered events, and level-triggered events are not allowed.
49. The data bit width should match.
50. Do not use real, time, realtime types.
51. It is recommended not to use the integer type.
52. The displacement variable must be a constant.
53. Avoid using asynchronous feedback circuits.
54. Non-blocking assignments are uniformly used in sequential logic statement blocks.
55. Blocking assignments are used in combinational logic blocks. ps: For 54 55, you need to understand the difference between blocking and non-blocking. In a non-blocking assignment statement, the expression on the right-hand side is not immediately passed to the left-hand side after the calculation, but will be passed to the left-hand side just before the next event is triggered, and they are parallel. That is to say, all the expressions on the right end are calculated when the valid edge of the clock arrives, and the value is assigned to the left end at the same time until the next valid edge of the clock arrives. It can be imagined that it is just right for the description of clock edge triggering, so it is used in sequential logic. Blocking assignment statements are passed to the left-hand side immediately after each expression on the right-hand side is calculated, and the following expressions can only be executed after the preceding expressions are completed. So it is a serial process, and combinatorial logic needs such an expression.
56. Non-blocking assignment statements do not add unit delay, especially when assigning variables of register type.
57. Integer constant base format cannot have '? '.
58. Strings cannot contain control characters (such as CTRL chains).
59. Empty sequential circuit blocks and illegal always structures are prohibited.
60. Do not introduce drive strength and delay in continuous assignment statements.
61. Do not define drive strength, charge retention strength and delay for variables of type net, n_input, n_output, enable_gate.
62. The use of trireg (connection with charge retention properties) NET type definition is prohibited.
63. The use of tri0, tri1, triand and trior connections is prohibited.
64. The initial structure cannot be included in the RTL-level code, nor can any signal be initialized and assigned. It should be initialized by reset.
65. Do not use assign, deassign, force, release and other statements in procedural statements.
66. Don't use the wait statement.
67. Do not use fork join blocks.
68. Do not assign values to the connection (net) of the driver type supply0 and supply1.
69. Macro_module is not used in the design.
70 Do not instantiate gate-level cells in RTL code, especially the following cells: CMOS switches, RCMOS switches, NMOS switches, PMOS switches, RNOMS switches, RPMOS switches, trans bidirectional switches, rtrans bidirectional switches, tranif0,tranif1,rtranif0,rtranif1, pull_gate.
71. Don't use the specify module.
Some of these rules I haven't figured out yet, and when more practical applications appear, there should be a sudden realization that practice is the only criterion for testing truth.