A summary record of the pits encountered in verilog programming

This is an article that is updated at any time. If you encounter a pit, you will record it. Come on!

1. Do not assign values ​​to the same variable in two always blocks. Otherwise there will be conflicts and errors
2. Try to use non-blocking assignment (<=) in sequential circuits, blocking assignment (=) in combinatorial logic, and assign statements only with "=".