[Original] Specification the Verilog programming code (personal)

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This article will be divided into three parts, the first part of the code feel comfortable programming style, the second part is the first part of some additional explanation. The third part is the record I made when reading a related article, summed up the first part for refining. Readers first and second part is enough, who are interested are also welcome to browse third part.

V programming specifications finishing

About naming

Common

1. Block / signal names try to use all lowercase letters (save in exceptional circumstances).
2. Modules / signal names should use meaningful words represent.

3. Word in connection with an underscore symbol "_."

   Module named

4. A module is generally placed in a file, the file name, module name remains the same.

5. Control module name length of 20 characters.

   Signal name

6. In order to avoid signal identifier name is too long, the appropriate use of shorthand.
7. Constant is defined using uppercase letters (full caps / first letter capitalized).
8. Active-low signal, thereafter adding the suffix "_n".
9. Tri-state signal, thereafter adding the suffix "_z".

10. The beat signal register, add the suffix "_r" thereafter. (The number of times not to use "_reg" willing to be part of the synthesizer will generate its own signal x_reg signals may cause some confusion)

About comments

Common

1. As required notices, can increase code readability, portability, maintainability.

2. Code file occupies less than the entire portion should be 1/3.

   File Comments

3. Beginning of the file, before the module declaration requires a header comments.
4. Module name
5. Module features
6. Author

7. Modify the record, people should be included to modify, amend, change in time and other information.

   Code comments

8. Note the code line comment instead make use of paragraph Notes
9. Input and output ports, the need to declare the variable comments brief description of the role

10. Block (always block) required action explanatory notes, further comment is required to increase ranging article described.

About writing

1. Before and after the special symbols separated by spaces, increase code readability.
2. Tab often used to align some of the symbols of the symbol, the symbol is set as Tab 4 spaces.
3. If judgment statement parentheses, separated by white space before and after the appropriate brackets.
4. Multi-level nested if ... else, and strictly ensure the alignment indentation.
5. When you use begin ... end, begin with the following statement (on the same line), reducing the number of rows. Additional examples illustrate the visible part of the relevant description.
6. Used strictly ".signal ()" of the embodiment is performed when the transmission parameters.
7. Tri-state logic may be used at the top level, the sub-modules to avoid using tri-state signal.
8. case structure needs to be done full-case.

Additional information

A description, commonly abbreviated

Description II No

Read the excerpt personal note

In style, many places have consistency, repeating section does not repeat.

1. Each module is generally present in a separate file, generally the module name, the file name is consistent.
2. Each file should contain the necessary comments at the beginning, it should contain the following sections:
   1. Year Name and Company
   2. Author
   3. file name
   4. It's not played
   5. Top-level module
   6. Module Name and Description
   7. Modify records
3. If there are no special circumstances, the module name and signal name all lowercase letters.
4. Constant definitions ( `define) and (parameter) in uppercase (capital portion or all upper case). Parameter name less than 20 letters.
5. C language identifier conventional manner using word symbol underscore "_" connections, such data_size. And the need to use some features of the object identifier Meaning reaction.
6. In order to avoid too long identifier, certain abbreviations may be used, such as write them becomes wt.
7. Tab symbols and spaces suitable tabulation symbols, Tab tabs defined as four spaces.
8. Should be used before and after the special characters separated by spaces, such as: a <= a + 1'b1;
9. There parentheses determine the conditions, then the front and rear brackets need space.
10. Multi-level nested, each layer requires strict alignment, begin ... end to strictly aligned.
11. Comment is necessary to increase the readability and portability, annotate content should be less than 30% of the whole.
12. For FSM variables, naming in ,
13. Use comments for port declarations (input and output), Use comments for internal signal declarations (wire or reg), Use comments for functional sections (always block).
14. Replace paragraph comment "/ multi-use" // "line comments the way ... /." Comments can be used at the beginning of paragraphs file comments.
15. When adding annotation described embodiment, and uses. () Example of embodiment.
16. Promptly remove dead code
17. Each line declares a variable
18. Try to correspond to the line width.
19. A low level signal, the signal suffix "_n".
20. Descending defined vector using the effective bit order, least significant bit 0.
21. Prefix clock signal "clk", the reset signal prefix "rst".
22. Tri-state signal added suffix "_z", reg register beat signal using the suffix "_r".
23. You can not use the code in VHDL and Verilog reserved words.
24. Tri-state logic may be used at the top level, avoiding the use of sub-modules.