Verilog programming - screening the largest and second largest values

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introduction

Among the questions of Haikang's practice written test this year, there is a programming question, which is about screening the maximum and second maximum values ​​in the input data. Make a timely note here.

topic description

Serially input a data sequence, and it is required to output the largest two numbers when only one traversal of this sequence is performed. Improve the following code:

module top2_sort #(
parameter DWIDTH = 8
)(
input               clk,
input               rst_n,
input               srst,
input [DWIDTH-1:0]  din,
input               din_vld,
output reg [DWIDTH-1:0] dout_top1,
output reg [DWIDTH-1:0] dout_top2,

output reg              doubt_vld
    );

//待完善
//=================================
endmodule

problem solving

I just got this topic, and all I thought about was how to get the maximum value, so how can the second maximum value be obtained after the sequential traversal?

First consider how to obtain the maximum value. This is simple. Every time data is input, compare the relationship between the input data and the current maximum value. If the input data is greater than the current maximum value, then the next clock cycle will use the input data to update the maximum value.

In fact, the second largest value only needs to be in,

1. When the condition for updating the maximum value is met, the current maximum value is given as the next largest value;

2. When the input data is greater than the current second largest value but not greater than the current largest value, update the second largest value;

According to this idea, the largest first N numbers of the input sequence can be obtained.

programming

Design code:

// ========================================================================
// 功能描述：-1- 找出输入序列的最大值 次大值
// 作者：Xu Y. B.
// 时间：2023-05-08
// ========================================================================


`timescale 1ns / 1ps

module top2_sort #(
parameter DWIDTH = 8
)(
input 							clk,
input 							rst_n,
input 		[DWIDTH-1:0]		din,						
input 							din_vld,						
output reg [DWIDTH-1:0] 		dout_top1,						
output reg [DWIDTH-1:0] 		dout_top2,						
output reg  					doubt_vld	
    );


always @ (posedge clk)
begin
	if(~rst_n)
	begin
		dout_top1 <= 0;
		dout_top2 <= 0;
	end
	else if(din_vld && (din > dout_top1))
	begin
		dout_top1 <= din;
		dout_top2 <= dout_top1;		
	end
	else if(din_vld && (din > dout_top2))
	begin
		dout_top2 <= din;
	end
end

always @ (posedge clk)
begin
	if(~rst_n)
	begin
		doubt_vld <= 1'b0;
	end
	else
	begin
		doubt_vld <= din_vld;
	end
end


endmodule

Simulation code:

// ========================================================================
// 功能描述：-1- 仿真验证模块 top2_sort 的功能
// 作者：Xu Y. B.
// 时间：2023-05-08
// ========================================================================



`timescale 1ns / 1ps

module tb_top2_sort();
parameter 	DWIDTH 		= 		8;

reg 							clk;
reg 							rst_n;
reg 		[DWIDTH-1:0]		din;						
reg 							din_vld;

wire 		[DWIDTH-1:0] 		dout_top1;						
wire 		[DWIDTH-1:0] 		dout_top2;						
wire  							doubt_vld;

initial clk = 1'b0;
always #10 clk = ~clk;

initial
begin
	rst_n   <= 1'b0;
	din     <= 0;
	din_vld	<= 0;
	#103;
	@(posedge clk)
	rst_n   <= 1;
	#103;
	@(posedge clk)
	din     <= 56;
	din_vld	<= 1;	

	@(posedge clk)
	din     <= 12;

	@(posedge clk)
	din     <= 109;

	@(posedge clk)
	din     <= 13;

	@(posedge clk)
	din     <= 1;

	@(posedge clk)
	din     <= 192;

	@(posedge clk)
	din     <= 127;

	@(posedge clk)
	din     <= 101;

	@(posedge clk)
	din     <= 189;

	@(posedge clk)
	din     <= 133;

	@(posedge clk)
	din     <= 145;

	@(posedge clk)
	din     <= 92;

	@(posedge clk)
	din     <= 44;

	@(posedge clk)
	din     <= 56;

	@(posedge clk)	
	din_vld	<= 0;	

	#102;
	$finish;
end

top2_sort #(
		.DWIDTH(DWIDTH)
	) INST_top2_sort (
		.clk       (clk),
		.rst_n     (rst_n),
		.din       (din),
		.din_vld   (din_vld),

		.dout_top1 (dout_top1),
		.dout_top2 (dout_top2),
		.doubt_vld (doubt_vld)
	);

endmodule

Simulation results:

 

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If you have other implementation ideas, I hope you can leave a message in the comment area to exchange~