Introduction to common data types in SystemVerilog

1. Common data types

1) bit byte(8) int(32) shortint(16) longint(64) variable type;
2) logic defines variable, four states 0 1 ZX, instead of reg, wire;
3) void type means no storage;
4) var The keyword indicates that the object is a variable, such as var logic[7:0] a;
5) static variable static automatic variable automatic
6) user uses typedef to customize the type
7) enumerated data type enum

Second, the use of enumeration type enum

module  FSM(input  logic clock, resetN，
 			output logic [3:0]  control);

	enum logic[2:0] {
    
    WAITE=3’b001,LOAD=3’b010,
	                             READY=3’b100}  State, Next;
	
	always @(posedge clock, negedge resetN)
	   if(!resetN) State <= WAITE;
	   else  State <= Next;
	
	always_comb begin
	   $display(“\n Current state is %s (%b)”, State.name, State);
	   case (State)
	       WAITE:  Next = LOAD;
	       LOAD:   Next = READY;
	       READY:  Next = WAITE;
	   endcase
	   $display(“Next state will be %s (%b)”, Next.name,Next);
	end
    
    assign control = State;

endmodule

Three, the introduction of structure struct

Structure struct is a variable set representation, which can include any data type, and can collect variables, constants, and custom types of different types and sizes:

Define structure

  struct {
    
    
        int   a,b;
        opcode_t opcode;  //用户自己定义类型
        logic [23:0] address;
        bit     error;
     } Instruction_Word (结构体名)；
  
  instruction_word_t IW

Reference structure:

<structure name>.<variable name>, such as:
Instruction_Word.address;

Structure assignment:

instruction_word_t IW = ’{100,3,8’hff,0};

always @()
IW.a = 100; IW.b = 5; IW.opcode = 8’hff; IW.address=0;

Four, union introduction

The union data type is similar to struct, but there are some differences in the memory allocation mechanism. Union can reduce storage.

Define the consortium

typedef  union {
    
    
        int   a;
        int   unsigned  u；
   } data_t (联合体名)；

data_t data;

Citing the consortium:

<
Combination name>.<variable name> such as data.a;

Five, the use of struct and union

package

package definitions;
  typedef enum {
    
    ADD,SUB,MULT,DIV,SL,SR} opcode_t;
  typedef enum {
    
    UNSIGNED, SIGNED} operand_type_t;
  typedef union packed {
    
     logic[31:0]  u_data; 
                                        logic signed [31:0] s_data; } data_t;
  typedef struct packed {
    
    
               opcode_t  opc;
               operand_type_t   op_type;
               data_t        op_a;
               data_t        op_b; } instr_t;
endpackage

struct packed represents a compressed structure, as a member of a vector storage structure.

RTL

import definitions:: *;
module  instruction_register(
   output  instr_t[0:31]  instr_reg,  
   input  data_t     operand_a,
   input  data_t     operand_b,
   input  operand_type_t  op_type,
   input  opcode_t    opcode,
   input  logic[4:0]    write_pointer );
always @(write_pointer) begin
   instr_reg[write_pointer].op_type = op_type;
   instr_reg[write_pointer].opc = opcode;
   if(op_type ==SIGNED) begin
        instr_reg[write_pointer].op_a.s_data = operand_a.s_data;
        instr_reg[write_pointer].op_b.s_data = operand_b.s_data;  end
   else begin
        instr_reg[write_pointer].op_a.u_data = operand_a.u_data;
        instr_reg[write_pointer].op_b.u_data = operand_b.u_data;  end
   end
endmodule

testbench

import definitions:: *;

module  tb_instruction_register();
	instr_t[0:31]  instr_reg;
	data_t operand_a=32'h0,operand_b=32'h0;
	operand_type_t op_type = UNSIGNED;
	opcode_t opcode = ADD;
	logic[4:0] write_pointer = 5'd0;
	logic clock = 1'b0;
	always #2 clock = ~clock;
	always_ff@(posedge clock)
	  begin
	    operand_a = {
    
    $random}%32;
	    operand_b = {
    
    $random}%32;
	    
	    if(write_pointer <= 5'h1f)
	      write_pointer += 1'b1;
	    else
	      write_pointer = 5'd0;
		
		if(write_pointer > 5'h0f)
	      opcode = SUB;
	    else
	      opcode = ADD;
	  end
	
	instruction_register n1(
	   instr_reg,
	   operand_a,
	   operand_b,
	   op_type,
	   opcode,
	   write_pointer );

endmodule