Glossary
1. Superscalar pipeline
Answer: Several instructions are started at the same time and enter the pipeline independently for execution.
That is: each clock cycle emits multiple instructions, there are multiple sets of instruction fetching components and instruction decoding components, and multiple instructions are executed at the same time, so there should be multiple execution components. Superscalar pipeline is a way of multi-instruction issuance.
2. Fast Form (TLB)
Answer: Use a special cache to keep track of the recently used page table entries. Page table entries are mainly used for address translation, because the speed of looking up page table entries in TLB is very fast, so TLB also becomes a fast table. TLB is usually very small, and generally uses full-association or group-association.
3. Interrupt vector.
Answer: Each interrupt source has a handler. This handler is called an interrupt service program, and its entry address is called an interrupt vector.
4.CPI
Answer: The average number of clock cycles per instruction
5. Right order
Answer: When adding and subtracting floating-point numbers, the operation performed before the addition and subtraction of the mantissa is called the order. When aligning the order, it is necessary to compare the size of the two orders. The mantissa of the smaller number moves to the right, and the order code increases. Shift the order code to the right and add 1 until the order codes of the two numbers are equal.
6. What are the stages of a complete interruption process?
Answer: A complete interrupt process includes: interrupt request, interrupt arbitration, interrupt response, interrupt processing and return.
8. Redundant Array of Disks (RALD)
Answer: j Organize multiple independently operated disks into a disk array in a certain way to increase capacity, and use multi-body cross technology similar to the main memory to store data on multiple disks, which can make these disks work in parallel To improve data transmission speed, and use redundant disk technology to improve system reliability.
9. Instruction cycle
Answer: The time between fetching one instruction and executing to fetching the next instruction. That is, the entire time it takes for an instruction to be read from the memory to the completion of its execution, including instruction fetching, instruction decoding, computer operand address, operand fetching, calculation, result storage, interrupt detection, etc.
10. Program status word (PSW)
Answer: A binary bit sequence that represents the running state of the program. Generally include flag information reflecting the result of instruction execution (such as carry flag, overflow flag, symbol flag, etc.) and some set status information (such as interrupt enable/disable flag, management program/user program, etc.)