Table of contents
1. Computer structure
Host:Main storage (memory), CPU (operator/controller).
Peripherals: Auxiliary memory (external storage, auxiliary storage) , IO (input device/output device).
Bus: data bus, control bus, address or instruction bus.
2.CPU composition
CPU is composed ofoperator and controller, which is the abbreviation of central control unit.
2.1 Operator
① Arithmetic logic unit ALU: arithmetic operations and logical operations on data.
② Accumulation register AC: A general-purpose register that provides a work area for the ALU for temporary storage of data.
③ Data buffer register DR: Temporarily stores instructions or data when writing to memory.
④ Status condition register PSW: stores status flags and control flags.
(Controversy: some also classify it as a controller)
2.2 Controller
① Program counter PC: Stores the address of the next instruction to be executed.
② Instruction register IR: stores the instruction to be executed.
③ Instruction decoder ID: Analyze and interpret the opcode field in the instruction.
④ Timing component: Provides timing control signals.
example:
Select A; the counter will save the address of the next instruction to be executed.
3. Von Neumann structure and Harvard structure
3.1 Von Neumann structure
The von Neumann structure, also known as the Princeton structure, is a memory structure that combines program instruction memory and data memory.
Features:
1. Generally used for PC processors, such as I3, I5, and I7 processors.
2. Instructions and data memory are merged together.
3. Both instructions and data are transmitted through the same data bus.
3.2 Harvard Structure
The Harvard architecture is a memory structure that separates program instruction storage and data storage. The Harvard architecture is a parallel architecture. Its main feature is to store programs and data in different storage spaces. That is, the program memory and data memory are two independent memories, and each memory is independently addressed and accessed independently.
Features:
1. Generally used in embedded system processors (DSP);Digital signal processing (DSP, Digital Signal Processing).
2. Instructions and data are stored separately and can be read in parallel, resulting in a higher data throughput rate.
3. There are 4 buses; data bus and address bus for instructions and data.
Example 1:
Select B; Core i3, i5, and i7 belong to von Neumann; FPGA is a programmable logic device and has no special architectural classification; GPU (graphics processor) There is no such thing as architectural partitioning.
Example 2:
Choose A; Big data processing requires clusters, and small chips are not very suitable for systems with large computational loads.