In the process of learning FPGA, pay attention to the use of FPGA skills in the process of learning. It is strongly recommended to try to design an SDRAM controller instead of using an IP core.
Learning SDRAM controller design can give you a lot of knowledge.
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Better use of state machines to precisely control timing.
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Learn the necessary skills in high-speed design, that is, the timing constraint method, the reading method of timing report, the basic skills of finding timing problems, the rational design of reset scheme and clock scheme, how to optimize the code to improve the highest working clock of the system, and the writing method of testbench.
Writing an sdram controller can still exercise many typical skills. It is worth spending time thinking and trying, and the price/performance ratio is desirable.
Design Flow:
See documentation.
Implement the logic of the sdram controller. Many public tutorials have guidance on how to implement basic functions, in different ways, you can refer to them; then you can think about how to improve the performance by yourself.
Write a test module, cooperate with the simulation model, verify whether the written logic is correct, and the read can be read as expected, and speed is not pursued at this stage.
If the frequency is not enough, add pipelines, cut the combination chain, parallelize, etc., improve the logic and increase the speed.
Study the timing constraints and make further optimizations to make it run on the board.
The sdram controller should now work.
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