verilog led 消抖计数器

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2021/11/03 21:30:16
// Design Name: 
// Module Name: key_top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module key_top(
    input sys_clk_p,
    input sys_clk_n,
    input rst_n,
    input key,
    output reg[3:0] led
    );
    wire sys_clk;
    IBUFDS sys_clk_ibufgds(
        .O(sys_clk),
        .I(sys_clk_p),
        .IB(sys_clk_n)
    );
    parameter ms_1 = 200_000;
    reg[31:0] timer;
	reg key_rsp;
    always @(posedge sys_clk or negedge rst_n)
    begin
        if(!rst_n)
        begin
            led<=4'b1111;
            timer<=0;
			key_rsp<=0;
        end
        else if (sys_clk)
        begin
            if(key) //按键未按下
			begin
				key_rsp<=0;
				timer<=0;
			end
			else
			begin
				if(!key_rsp)
				begin
					timer<=timer+1;
					if(timer==ms_1*80)
					begin
						key_rsp<=1;
						led<=led-1;
					end
				end
			end
        end  
    end
    ila_0 myila(
        .clk(sys_clk),
        .probe0(key),
        .probe1(led[3]),
        .probe2(led[2]),
        .probe3(led[1]),
        .probe4(led[0])
    );
endmodule