目录
一、顶层程序
module Freq_Counter(clk,bit,seg,in,ts_50M,ts_10M,ts_1M,ts_100k,ts_10k,ts_1k);//顶层文件,仿真时加入clk_400Hz
input clk,in;//仿真时加入clk_400Hz、in在仿真时是输入信号 //输入端口定义
output ts_50M,ts_10M,ts_1M,ts_100k,ts_10k,ts_1k;
output [7:0]bit,seg;
wire clk_400Hz;//仿真时需注释此行
wire [3:0]Data0,Data1,Data2,Data3,Data4,Data5,Data6,Data7;
wire [3:0]data0,data1,data2,data3,data4,data5,data6,data7;
wire en,rst,lat;
test_sig U0 (.clk(clk), //测试信号
.ts_50M(ts_50M),
.ts_10M(ts_10M),
.ts_1M(ts_1M),
.ts_100k(ts_100k),
.ts_10k(ts_10k),
.ts_1k(ts_1k));
clk_div U1(.clk_in(clk), //显示屏400Hz信号
.clk_out(clk_400Hz));
Freq_Ctr1 U2(.clk(clk), //控制信号的产生
.en(en), //使能信号
.rst(rst), //清零信号****
.lat(lat)); //锁存信号****
counter U3 (.clk(in), //8位BCD计数器,仿真时将in改为clk
.en(en),
.rst(rst),
.Q0(data0),
.Q1(data1),
.Q2(data2),
.Q3(data3),
.Q4(data4),
.Q5(data5),
.Q6(data6),
.Q7(data7));
data_store U4(.lat(lat), //32位锁存器,锁存信号
.in0(data0),
.in1(data1),
.in2(data2),
.in3(data3),
.in4(data4),
.in5(data5),
.in6(data6),
.in7(data7),
.out0(Data0),
.out1(Data1),
.out2(Data2),
.out3(Data3),
.out4(Data4),
.out5(Data5),
.out6(Data6),
.out7(Data7));
LED U5(.clk(clk_400Hz),
.LED_Bit(bit),
.LED_SEG(seg),
.Data0(Data0),
.Data1(Data1),
.Data2(Data2),
.Data3(Data3),
.Data4(Data4),
.Data5(Data5),
.Data6(Data6),
.Data7(Data7));
endmodule
二、系统产生测试信号单元
module test_sig(clk,ts_50M,ts_10M,ts_1M,ts_100k,ts_10k,ts_1k);
input clk;
output ts_50M,ts_10M,ts_1M,ts_100k,ts_10k,ts_1k;
reg ts_10M,ts_1M,ts_100k,ts_10k,ts_1k;
reg [50:0] div_cnt1,div_cnt2,div_cnt3,div_cnt4,div_cnt5;
assign ts_50M=clk; //输出为50MHz
always@(posedge clk) //输出为10MHz
begin
if(div_cnt1==(3/2))
begin
div_cnt1<=0;
ts_10M<=~ts_10M;
end
else
begin div_cnt1<=div_cnt1+50'd1;
end
end
always@(posedge clk) //输出为1MHz
begin
if(div_cnt2==(24)) //50MHz/1MHz/2=50/2=25
begin
div_cnt2<=0;
ts_1M<=~ts_1M;
end
else
begin div_cnt2<=div_cnt2+50'd1;
end
end
always@(posedge clk) //输出为100kHz
begin
if(div_cnt3==(249)) //50MHz/100kHz/2=500/2=250
begin
div_cnt3<=0;
ts_100k<=~ts_100k;
end
else
begin div_cnt3<=div_cnt3+50'd1;
end
end
always@(posedge clk) //输出为10kHz
begin
if(div_cnt4==(2499)) //50MHz/10kHz/2=5000/2=2500
begin
div_cnt4<=0;
ts_10k<=~ts_10k;
end
else
begin div_cnt4<=div_cnt4+50'd1;
end
end
always@(posedge clk) //输出为1kHz
begin
if(div_cnt5==(24999)) //50MHz/10kHz/2=50000/2=25000
begin
div_cnt5<=0;
ts_1k<=~ts_1k;
end
else
begin div_cnt5<=div_cnt5+50'd1;
end
end
endmodule
三、400HZ分频器单元
//400Hz分频器
//在仿真时将第10行中的Q==n做改变,如:令n=4,当输入信号是50MHz时,输出为10MHz;
module clk_div(clk_in,clk_out);
input clk_in;
output reg clk_out;
reg[23:0] Q;
always@(posedge clk_in)
begin
if(Q==62499)//[(50M/400)/2]-1
begin
Q<=0;
clk_out<=~clk_out;
end
else
begin
Q<=Q+23'd1;
end
end
endmodule
四、控制信号单元
module Freq_Ctr1(clk,en,rst,lat);//控制信号的产生
input clk;//输入的时钟信号
output reg en,rst,lat;//分别为使能信号,清零信号,锁存信号
reg [26:0]ctrl_cnt;//计数用
always@(posedge clk)//从0到53000000的计数器
begin
if(ctrl_cnt==53000000)//53000000
begin
ctrl_cnt<=0;
end
else
begin
ctrl_cnt<=ctrl_cnt+26'd1;
end
end
always@(ctrl_cnt)//三种控制信号
begin
//给en,rst,lat赋初值
en<=0;
rst<=0;
lat<=0;
begin//en使能信号的产生,1为有效值
if(ctrl_cnt<50000000)//50000000
begin
en<=1;
end
else
begin
en<=0;
end
end
begin//lat锁存器控制,1为有效值
if(ctrl_cnt>50000100&&ctrl_cnt<50000100)//50000100 50000200
begin
lat<=1;
end
else
begin
lat<=0;
end
end
begin//rst清零器控制,1为有效值
if(ctrl_cnt>50000300&&ctrl_cnt<50000400)//50000300 50000400
begin
rst<=1;
end
else
begin
rst<=0;
end
end
end
endmodule
//仿真时:将关键数字改为530;500;501;510;511;520
五、8位十进制计数器
module counter(clk,en,rst,Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7);//8位BCD计数器
input clk,en,rst;//分别为时钟信号,使能信号,清零信号
output[3:0]Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7;
//reg[3:0]Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7;此处不能使用reg寄存器类型。
wire Cy0,Cy1,Cy2,Cy3,Cy4,Cy5,Cy6,Cy7;
CNT10 U1(.CLK(clk),.ENABLE(en),.RESET(rst),.FULL(Cy0),.Q(Q0)); //个位
CNT10 U2(.CLK(clk),.ENABLE(Cy0),.RESET(rst),.FULL(Cy1),.Q(Q1)); //十位
CNT10 U3(.CLK(clk),.ENABLE(Cy0&&Cy1),.RESET(rst),.FULL(Cy2),.Q(Q2)); //百位
CNT10 U4(.CLK(clk),.ENABLE(Cy0&&Cy1&&Cy2),.RESET(rst),.FULL(Cy3),.Q(Q3)); //千位
CNT10 U5(.CLK(clk),.ENABLE(Cy0&&Cy1&&Cy2&&Cy3),.RESET(rst),.FULL(Cy4),.Q(Q4)); //万位
CNT10 U6(.CLK(clk),.ENABLE(Cy0&&Cy1&&Cy2&&Cy3&&Cy4),.RESET(rst),.FULL(Cy5),.Q(Q5)); //十万位
CNT10 U7(.CLK(clk),.ENABLE(Cy0&&Cy1&&Cy2&&Cy3&&Cy4&&Cy5),.RESET(rst),.FULL(Cy6),.Q(Q6)); //百万位
CNT10 U8(.CLK(clk),.ENABLE(Cy0&&Cy1&&Cy2&&Cy3&&Cy4&&Cy5&&Cy6),.RESET(rst),.FULL(Cy7),.Q(Q7)); //千万位
endmodule
5.1一位十进制计数器
module CNT10(CLK,ENABLE,RESET,FULL,Q);
input CLK,ENABLE,RESET;
output FULL;
output [3:0]Q;
reg[3:0]QINT;
always@(posedge RESET or posedge CLK)
begin
if(RESET )
QINT=4'B0000;
else if(ENABLE)
begin
if(QINT==9)
QINT=4'B0000;
else
QINT=QINT+4'B1;
end
end
assign Q=QINT;
assign FULL=(QINT==9)?1'B1:1'B0;
endmodule
六、锁存器单元
module data_store(lat,in0,in1,in2,in3,in4,in5,in6,in7,
out0,out1,out2,out3,out4,out5,out6,out7); //定义输入输出端口
input lat; //定义锁存信号
input[3:0]in0,in1,in2,in3,in4,in5,in6,in7; //定义输入信号的长度
output reg [3:0]out0,out1,out2,out3,out4,out5,out6,out7; //定义输出信号的长度
always@(lat)
begin
if(lat==1) //定义当为高电平时,该锁存器开始工作,锁存信号
begin
out0<=in0;
out1<=in1;
out2<=in2;
out3<=in3;
out4<=in4;
out5<=in5;
out6<=in6;
out7<=in7;
end //输出信号赋值给输入信号
end
endmodule
//该器件为32位锁存器
七、LED控制顶层程序
module LED(clk,LED_Bit,LED_SEG,Data0,Data1,Data2,Data3,Data4,Data5,Data6,Data7);//仿真时将clk改为clk_400Hz
input clk; //仿真时将clk改为clk_400Hz
input [3:0]Data0,Data1,Data2,Data3,Data4,Data5,Data6,Data7;
output [7:0] LED_Bit;
output [7:0] LED_SEG;
wire clk_400Hz; //仿真时注释
wire[2:0]scan_cnt;
wire[3:0]Data_BCD;
clk_div U1(.clk_in(clk), //输入信号(50MHz)
.clk_out(clk_400Hz)); //输出的供显示屏使用400Hz信号
cnt U2(.clk(clk_400),
.Q0(scan_cnt[0]),
.Q1(scan_cnt[1]),
.Q2(scan_cnt[2])
);
decode3_8 U3 (.A(scan_cnt[0]),
.B(scan_cnt[1]),
.C(scan_cnt[2]),
.Y0(LED_Bit[7]),
.Y1(LED_Bit[6]),
.Y2(LED_Bit[5]),
.Y3(LED_Bit[4]),
.Y4(LED_Bit[3]),
.Y5(LED_Bit[2]),
.Y6(LED_Bit[1]),
.Y7(LED_Bit[0])
);
mux8_1 U4( .A0(scan_cnt[0]),
.A1(scan_cnt[1]),
.A2(scan_cnt[2]),
.D0(Data0),
.D1(Data1),
.D2(Data2),
.D3(Data3),
.D4(Data4),
.D5(Data5),
.D6(Data6),
.D7(Data7),
.Y(Data_BCD)
);
BCD_7seg U5(.D0(Data_BCD[0]),
.D1(Data_BCD[1]),
.D2(Data_BCD[2]),
.D3(Data_BCD[3]),
.a(LED_SEG[0]),
.b(LED_SEG[1]),
.c(LED_SEG[2]),
.d(LED_SEG[3]),
.e(LED_SEG[4]),
.f(LED_SEG[5]),
.g(LED_SEG[6]),
.h(LED_SEG[7]),
);
endmodule
7.1 400Hz分频器
//400Hz分频器
//在仿真时将第10行中的Q==n做改变,如:令n=4,当输入信号是50MHz时,输出为10MHz;
module clk_div(clk_in,clk_out);
input clk_in;
output reg clk_out;
reg[23:0] Q;
always@(posedge clk_in)
begin
if(Q==62499)//[(50M/400)/2]-1
begin
Q<=0;
clk_out<=~clk_out;
end
else
begin
Q<=Q+23'd1;
end
end
endmodule
7.2 计数器程序
module cnt(clk,Q0,Q1,Q2);
input clk;
output Q0,Q1,Q2;
wire nQ0,nQ1,nQ2;
trig U1(.clk(clk),.D(nQ0),.Q(Q0),.nQ(nQ0));
trig U2(.clk(nQ0),.D(nQ1),.Q(Q1),.nQ(nQ1));
trig U3(.clk(nQ1),.D(nQ2),.Q(Q2),.nQ(nQ2));
endmodule
7.2.1 D触发器
module trig(clk,D,Q,nQ);
input clk,D;
reg Q,nQ;
output Q,nQ;
always @(posedge clk)
//shangshengyan//
//negedge//
begin
Q<=D;
nQ<=!D;
//<=fuzhi//
end
endmodule
7.3 3_8译码器
module decode3_8(C,B,A,Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0);
input C,B,A;
output Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0;
reg Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0;
always @(C,B,A)
begin
if({C,B,A}==3'b000)
{Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0}=8'b1111_1110;
else if({C,B,A}==3'b001)
{Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0}=8'b1111_1101;
else if({C,B,A}==3'b010)
{Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0}=8'b1111_1011;
else if({C,B,A}==3'b011)
{Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0}=8'b1111_0111;
else if({C,B,A}==3'b100)
{Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0}=8'b1110_1111;
else if({C,B,A}==3'b101)
{Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0}=8'b1101_1111;
else if({C,B,A}==3'b110)
{Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0}=8'b1011_1111;
else
{Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0}=8'b0111_1111;
end
endmodule
7.4 数据选择器
module mux8_1(D0,D1,D2,D3,D4,D5,D6,D7,Y,A2,A1,A0);
input A2,A1,A0;
input [3:0]D0,D1,D2,D3,D4,D5,D6,D7;
output [3:0]Y;
reg [3:0]Y;
always @(A2,A1,A0)
begin
case ({A2,A1,A0})
3'b000:Y=D0;
3'b001:Y=D1;
3'b010:Y=D2;
3'b011:Y=D3;
3'b100:Y=D4;
3'b101:Y=D5;
3'b110:Y=D6;
3'b111:Y=D7;
default Y=D0;
endcase
end
endmodule
7.5 7位BCD码译码器
module BCD_7seg(D0,D1,D2,D3,a,b,c,d,e,f,g,h);
input D0,D1,D2,D3;
output a,b,c,d,e,f,g,h;
reg a,b,c,d,e,f,g,h;
always @(D3,D2,D1,D0)
begin
case({D3,D2,D1,D0})
4'd0:{h,g,f,e,d,c,b,a}=8'b1100_0000;
4'd1:{h,g,f,e,d,c,b,a}=8'b1111_1001;
4'd2:{h,g,f,e,d,c,b,a}=8'b1010_0100;
4'd3:{h,g,f,e,d,c,b,a}=8'b1011_0000;
4'd4:{h,g,f,e,d,c,b,a}=8'b1001_1001;
4'd5:{h,g,f,e,d,c,b,a}=8'b1001_0010;
4'd6:{h,g,f,e,d,c,b,a}=8'b1000_0010;
4'd7:{h,g,f,e,d,c,b,a}=8'b1111_1000;
4'd8:{h,g,f,e,d,c,b,a}=8'b1000_0000;
4'd9:{h,g,f,e,d,c,b,a}=8'b1001_0000;
default:{h,g,f,e,d,c,b,a}=8'b1111_1111;
endcase
end
endmodule
八、引脚分配
九、模拟电路部分
9.1 整形电路
9.2放大电路