D型主从触发器module
//D_flip_flop
module flop(data,clock,clear,q,qb);
input data,clock,clear;
output q,qb;
nand #10 nd1(a,data,clock,clear),
nd2(b,ndata,clock),
nd4(d,c,b,clear),
nd5(e,c,nclock),
nd6(f,d,nclock),
nd8(qb,q,f,clear);
nand #9 nd3(c,a,d),
nd7(q,e,qb);
not #10 iv1(ndata,data),
iv2(nclock,clock);
endmodule
4Bit寄存器
//4Bit Reg with Clear
`include "Module_D_F.v"
module hardreg(d,clk,clrb,q);
input clk,clrb;
input[3:0] d;
output[3:0] q;
flop f1(d[0],clk,clrb,q[0],),//Why this ","//Answer no use "qb" but the "," must be Hold
f2(d[1],clk,clrb,q[1],),
f3(d[2],clk,clrb,q[2],),
f4(d[3],clk,clrb,q[3],);
endmodule
/*
as well Edit like this
module hardreg(d,clk,clrb,q);
input clk,clrb;
input[3:0] d;
output[3:0] q;
reg[3:0] reg_q;
always @ (posedge clk or posedge clrb)
begin
if(clrb)
reg_q<=0;
else
reg_q<=d;
end
endmodule
*/
测试文件：
`include "Module_D_F.v"
`include "hardreg.v"
module hardreg_top;
reg clock,clearb;
reg[3:0] data;
wire[3:0] qout;
`define stim #100 data = 4'b
event end_first_pass;
hardreg reg_4bit(.d(data),.clk(clock),.clrb(clearb),.q(qout));
initial
begin
clock=0;
clearb=1;
end
always #50 clock=~clock;
always @(end_first_pass)
clearb = ~clearb;
always @(posedge clock)
$display("at time %0d clearb = %b data=%d qout=%d",$time,clearb,data,qout);
initial
begin
repeat(4)
begin
data=4'b0000;
`stim 0001;
`stim 0010;
`stim 0011;
`stim 0100;
`stim 0101;
#200 ->end_first_pass;
end
$finish;
end
Endmodule
仿真波形1us：
发现有些不对的值，感觉整个波形不太对。
我的理解是，与非门具有延迟时间，所以波形延后了，
这一段是因为这个结构引起的
仿真二选一选择器
模块
module mux2(d1,d2,clk,choose,q);
input d1,d2,clk,choose;
output q;
reg q;
always @(posedge clk)
begin
if(choose)
q<=d1;
else
q<=d2;
end
Endmodule
这里如果我将q<=d1改为q=d1，则会出现q一直为z高阻的状态。
测试模块
module test_mux2;
reg din1,din2,clkin,choosein;
wire qout;
mux2 m(.d1(din1),.d2(din2),.clk(clkin),.choose(choosein),.q(qout));
initial
begin
din1=0;
din2=1;
clkin = 0;
choosein = 0;
end
always #50 clkin = ~clkin;
always #70 choosein = ~choosein;
Endmodule
乘法器
关于上图的乘法器的传输延迟，我认为是从右上角的MU开始，呈网状分布至左下角，
8位计数器
计数器模块
module counter2(out,cout,data,load,cin,clk);
output[7:0] out;
output cout;
input[7:0] data;
input load,cin,clk;
reg[7:0] out;
reg cout;
//创建8位寄存器
reg[7:0] preout;
always @(posedge clk)
begin
out<= preout;
end
always @(out or data or load or cin)
begin
{cout,preout} = out+cin;//不管加不加载，都可以计算进位，这样可以提高性能，因为不必再检测加载
if(load)
preout = data;
end
endmodule
测试模块
module test_counter_1;
//module counter2(module counter2(out,cout,data,load,cin,clk););
reg clk,cin,load;
wire cout;
wire[7:0] out;
reg[7:0] data;
counter2 c(.out(out),.cout(cout),.data(data),.load(load),.cin(cin),.clk(clk));
initial
begin
#1 clk = 0;
#1 load= 0;
#1 cin = 1;
#1 data = 8'b0000_0000;
#1 load = 1;
end
initial
begin
#100 load = 0;
end
always #25 clk =~clk;
always #100 cin=~cin;
endmodule
仿真波形
比较器
比较器
module compare(equal,a,b);
input a,b;
output equal;
assign equal = (a==b?1:0);
Endmodule
测试模块
`timescale 1ns/1ns
`include "./compare_1.v"
module test_compare;
reg a,b;
wire equal;
initial
begin
a = 0;
b = 0;
#100 a=0;b=1;
#100 a=0;b=1;
#100 a=1;b=1;
#100 $stop;
end
compare com(.equal(equal),.a(a),.b(b));
Endmodule
仿真波形
1/2分频器
分频器
module half_clk(reset,clk_in,clk_out);
input clk_in,reset;
output clk_out;
reg clk_out;
always@(posedge clk_in)
begin
if(!reset) clk_out = 0;
else clk_out=~clk_out;
end
endmodule
测试模块
`timescale 1ns/100ps
`define clk_cycle 50
module top;
reg signal_clk,signal_reset;
wire signal_clk_out;
always #`clk_cycle signal_clk = ~signal_clk;
initial
begin
signal_clk = 0;
signal_reset = 1;
#10 signal_reset = 0;
#110 signal_reset = 1;
#600 signal_reset = 0;
#100000 $stop;
end
half_clk h(.clk_in(signal_clk),.reset(signal_reset),.clk_out(signal_clk_out));
endmodule
1/20分频器
仿真波形
分频器
module fdivision(RESET,F10MB,F500KB);
input F10MB,RESET;
output F500KB;
reg F500KB;
reg[7:0] j;
always@(posedge F10MB)
if(!RESET)
begin
F500KB<=0;
j<=0;
end
else
begin
if(j==19)
begin
j<=0;
F500KB<=~F500KB;
end
else
j<=j+1;
end
endmodule
测试模块
`timescale 1ns/100ps
`define clk_cycle 10
module division_Top;
reg F10MB;
reg RESET;
wire F500KB;
initial
begin
F10MB = 0;
RESET = 0;
#100 RESET =1;
end
always #`clk_cycle F10MB=~F10MB;
fdivision f(.F10MB(F10MB),.F500KB(F500KB),.RESET(RESET));
endmodule
总线串转并-并转串
S-P
`timescale 1ns/1ns
`define YES 1
`define NO 0
module S_P(data,Dbit_in,Dbit_ena,clk);
output[7:0] data;
input Dbit_in,clk;
input Dbit_ena;//字节位流使能输入口
reg[7:0] data_buf;
reg finish_in;
//reg link_S_P_ena;
reg[3:0] state;
parameter idle=4'b0000;
assign data=(finish_in)?data_buf:8'bz;
always @(negedge clk)
begin
if(!Dbit_ena)
begin
//link_S_P_ena <= `NO;
//data_in <=0;
state <=idle;
finish_in <=1;//Notice this is ok1 because when it is 1 P_S not work so S_P must work
end
else
case(state)
idle: begin
//link_S_P_ena<=`YES;
finish_in <=0;
data_buf[7] <=Dbit_in;
state <=4'd1;
end
4'd1: begin
data_buf[6] <=Dbit_in;
state <=4'd2;
end
4'd2: begin
data_buf[5] <=Dbit_in;
state <=4'd3;
end
4'd3: begin
data_buf[4] <=Dbit_in;
state <=4'd4;
end
4'd4: begin
data_buf[3] <=Dbit_in;
state <=4'd5;
end
4'd5: begin
data_buf[2] <=Dbit_in;
state <=4'd6;
end
4'd6: begin
data_buf[1] <=Dbit_in;
state <=4'd7;
end
4'd7: begin
data_buf[0] <=Dbit_in;
state <=4'd8;
end
4'd8: begin
state <=4'b1111;//结尾，state状态写作1111
finish_in <=1;
end
default:
begin
state <=4'dz;
finish_in <=0;
end
endcase
end
Endmodule
- S
/*
模块功能：
把在nGet_AD_data负跳变沿时刻后能维持约3个时钟周期的并行字节数据取入模块，
在时钟节拍下转换为字节的位流，并产生相应字节位流的有效信号。
*/
`define YES 1
`define NO 0
module P_S(Dbit_out,link_S_out,data,nGet_AD_data,clk);
input clk; //主时钟节拍
input nGet_AD_data; //负电平有效时取并行数据控制信号线
input[7:0] data; //并行输入的数据端口
output Dbit_out; //串行位流的输出
output link_S_out; //允许串行位流输出的控制信号
reg[3:0] state; //状态变量寄存器
reg[7:0] data_buf; //并行数据缓存器
reg link_S_out; //串行位流输出的控制信号寄存器
reg d_buf; //位缓存器
reg finish_flag; //字节处理已经结束的标志
assign Dbit_out = (link_S_out)?d_buf:0;
always@(posedge clk or negedge nGet_AD_data)
begin
if(!nGet_AD_data)//取到nGet_AD_data的负跳变沿，开始置位,所有的缓存器置零，标志位至为初始态
begin
finish_flag <=0;
link_S_out <=`NO;
d_buf <=0;
data_buf <=0;
state <=9;
end
else
//开始进入状态转换
case(state)
9: begin
data_buf <=data;
state <=10;
link_S_out <=`NO;
end
10: begin
data_buf <=data;
state <=0;
link_S_out <=`NO;
end
0: begin
d_buf <=data_buf[7];
state <=1;
link_S_out <=`YES;
end
1: begin
d_buf <=data_buf[6];
state <=2;
end
2: begin
d_buf <=data_buf[5];
state <=3;
end
3: begin
d_buf <=data_buf[4];
state <=4;
end
4: begin
d_buf <=data_buf[3];
state <=5;
end
5: begin
d_buf <=data_buf[2];
state <=6;
end
6: begin
d_buf <=data_buf[1];
state <=7;
end
7: begin
d_buf <=data_buf[0];
state <=8;
end
8: begin
finish_flag <=1;
link_S_out <=`NO;
state <=4'b1111;
end
default:begin
link_S_out <=`NO;
state<=4'b1111;
end
endcase
end
endmodule
-sys
//把两个独立的逻辑模块合并到一个可综合的模块中
//共用一条并行总线
`include "./P_S.v"
`include "./S_P.v"
module sys(databus,use_p_in_bus,Dbit_out,Dbit_ena,nGet_AD_data,clk);
input nGet_AD_data;//取并行数据的控制信号
input use_p_in_bus;//并行总线用于输入数据的控制信号
input clk;
inout[7:0] databus;//双向并行数据总线
output Dbit_ena;//总线串行字节流出的使能
output Dbit_out;//总线串行字节流出的字节
wire clk;
wire nGet_AD_data;
wire Dbit_ena;
wire Dbit_out;
wire[7:0] data;//这个是做什么用的
assign databus = (!use_p_in_bus)?data:8'bzzzz_zzzz;
P_S m0(.Dbit_out(Dbit_out),.link_S_out(Dbit_ena),.data(databus),.nGet_AD_data(nGet_AD_data),.clk(clk));
S_P m1(.data(data),.Dbit_in(Dbit_out),.Dbit_ena(Dbit_ena),.clk(clk));
Endmodule
测试模块
`timescale 1ns/1ns
`include "./sys.v"
module Top;
reg clk;
reg[7:0] data_buf;
reg nGet_AD_data;
reg D_Pin_ena;
wire[7:0] data;
wire clk2;
wire Dbit_ena;
assign data = (D_Pin_ena)?data_buf:8'bz;
initial
begin
clk=0;
nGet_AD_data=1;
data_buf=8'b1001_1111;
D_Pin_ena=0;
end
initial
begin
repeat(100)
begin
#(100*14+{$random}%23)nGet_AD_data=0;//取并行数据启动
#(112+{$random}%12)nGet_AD_data=1;//保持一段时间后，不再取并行数据
#({$random}%50)D_Pin_ena=1;//并行数据输入sys模块的使能信号有效
#(100*3+{$random}%5)D_Pin_ena=0;
#333 data_buf=data_buf+1;
#(100*11+{$random}%1000);
end
end
always #(50+$random%2)clk=~clk;//主时钟
sys ms(.databus(data),.use_p_in_bus(D_Pin_ena),.Dbit_out(Dbit_out),.Dbit_ena(Dbit_ena),.nGet_AD_data(nGet_AD_data),.clk(clk));
Endmodule
仿真波形
