1 verilog代码
`timescale 1ns / 1ps
module led(
//clock and reset
sys_clk , //input sys_clk
sys_reset , //input sys_reset
//o_led
o_led );//output o_led
input sys_clk ;//50MHz
input sys_reset ;
output o_led ;
reg o_led ;
reg [31:0] led_cnt ;
//led_cnt
always @(posedge sys_clk)begin
if(sys_reset)
led_cnt <= 'd0;
else if(led_cnt == 32'd50_000_000 - 1'b1)//1s
led_cnt <= 'd0;
else
led_cnt <= led_cnt + 'd1;
end
//o_led
always @(posedge sys_clk)begin
if(sys_reset)
o_led <= 'd0;
else if(led_cnt == 32'd50_000_000 - 1'b1)//1s
o_led <= ~o_led;
end
endmodule
2 结束语
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