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提取码：klzz
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2019/11/27 14:34:05
// Design Name:
// Module Name: level_adc
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module level_adc
(
input clk ,
input start,//two cycle width of "clk"
output sclk ,
output cs_n ,
input sdat ,
output[12:0] level,
output reg valid
);
//there will be one cycle ambiguity to truely start ADC sampling.
//since
reg div2= 1'b1;
always @ ( posedge clk )
div2 <= ~div2;
reg[13:0] length=0;
always @ ( posedge clk )
if(div2)
begin
length <= {length[12:0],start};
end
(* IOB="TRUE" *)
reg chip_sel=1'b1;
reg sclk_gat=1'b0;
always @ ( posedge clk )
if(div2)
if(length!=14'h0)
begin
chip_sel <= 1'b0;
end
else
begin
chip_sel <= 1'b1;
end
always @ ( posedge clk )
if(div2)
if({length[13:0],start}!=15'h0)
begin
sclk_gat <= 1'b1;
end
else
begin
sclk_gat <= 1'b0;
end
assign cs_n = chip_sel;
reg clk_gen=1'b0;
always @ ( posedge clk )
clk_gen <= div2 & sclk_gat;
assign sclk = clk_gen;
reg[11:0] sample=12'h0;
always @ ( posedge clk )
if(div2)
case(length)
14'h0004:#1 sample[00]<= sdat;
14'h0008:#1 sample[01]<= sdat;
14'h0010:#1 sample[02]<= sdat;
14'h0020:#1 sample[03]<= sdat;
14'h0040:#1 sample[04]<= sdat;
14'h0080:#1 sample[05]<= sdat;
14'h0100:#1 sample[06]<= sdat;
14'h0200:#1 sample[07]<= sdat;
14'h0400:#1 sample[08]<= sdat;
14'h0800:#1 sample[09]<= sdat;
14'h1000:#1 sample[10]<= sdat;
14'h2000:#1 sample[11]<= sdat;
default :#1 sample <=sample;//14'h0;
endcase
assign level = sample;
always @ ( posedge clk )
valid <= chip_sel & clk_gen;
endmodule