#script for Design Compiler
# Language : TCL
# Usage :
# 1) make sure the lib in the current directory
# 2) if you have the file .synopsys_dc.setup,
# set synopsys_dc_setup_file 1,
# if not, set synopsys_dc_setup_file 0
# 3) change Step 3 : Variables to what you want
# Especially : top module name, clock name,
# reset name, all files name, and period
# 4) typing dc_shell-t -f run_72.tcl | tee -i run.log
#
#========================================================
set synopsys_dc_setup_file 0
#-----------------------------------------------------
# Step 1 :
# Setting Up path and library：
# If you have edited the file .synopsys_dc.setup, then you can skip over this step
#-----------------------------------------------------
if { $synopsys_dc_setup_file == 0} {
set search_path [list /home/chanshi/dc/library/smic /home/chanshi/dc/rfid/source /home/chanshi/dc/script]
set target_library {typical.db}
#set target_library {CSM35OS142_typ.db};
# if you want use typical library,change to typical.db
#set link_library [list {*} ram_interp_typical_syn.db ram_458_typical_syn.db typical.db]
set link_library [list {*} $target_library]
}
#set symbol_library {csm18ic.sdb csm18io.sdb}
#set synthetic_library {dw_foundation.sldb};
# Design Ware
set command_log_file "command.log"
# ------------------------------------------------- ----
# the Step 2:
# the Compile Swithes
# -------------------------------------- ---------------
#set verilogout_no_tri to true;
# IF INOUT Used, Tri nET will bE Used
# netlist to ensure by the tri-state (Tri) logic statements into net (wire) does not appear in tri-state logic, difficult to read because some routing tool comprising tri, tran source language, netlist ASSIGN statement for "inout" type of port, DC generates and tran tri wire source language sentence, for the tri, also produce assign statement
set test_default_scan_style multiplexed_flip_flop
type provided # scan chain, may also be provided by the -style set_scan_configuration
sET link_force_case CASE_INSENSITIVE
# set link command is case-sensitive, the default is check_reference, is to determine whether the size of the module according to the format of the generated reference write sensitive, if it is vhdl format is not sensitive, if you are sensitive to verilog
define_name_rules VLSI_NET -allowed "a-zA-Z0-9_" -first_restricted "0-9_" -type net -max_length 256
define_name_rules VLSI_CELL -allowed "a-zA-Z0-9_" -first_restricted "0-9_" -type cell -max_length 256
define_name_rules VLSI_PORT -allowed "a-zA-Z0-9_" -first_restricted "0-9_" -type port -max_length 256
define_name_rules TAN_RULE -allowed "a-zA-Z0-9_" -first_restricted "0-9_\[]" -max_length 256 -map {{{"*cell*", "mycell"}, {"*-return", "myreturn"}}};
set hdlin_check_no_latch "true"
#设置如果推断出锁存器，是否报warning，默认是false，即不报。
set hdlin_merge_nested_conditional_statements "true"
# As the name suggests, whether the nest if fusion, the default value is false, that is, for each nested conditional statements if and case (if or case statement) are deduced in a selector, this approach is conducive to a these determination conditions late signal (late arriving signals) arranged nearest to the output from the selector (thereby helping to reduce the delay), if set to true, these selectors will be fused into a large selector, so that all the output of the distance to the selection signal are the same
# ------------------------------------------------- ----
# the Step 3:
# the Define the Variables
# -------------------------------------- ---------------
SET active_design "whole_modules";
# Top Module1 name
Source files.tcl;
# All the Source_Files the RTL (Verilog)
SET clock_name "CLK";
# the name of Clock
SET reset_name " RESET ";
# the Name of RESET
sET clk_period 70.0
# set clock cycle, noted with a decimal point, thus calculated values with decimal point, or a number less than 1 is displayed as 0
# Desired clock period = 1000 / Frequence
sET clk_uncertainty_setup [expr clk_period / 200];
# set the clock uncertainty, just to set the relative uncertainty for the establishment of the time, is likely to advance the rising edge of the clock clk_uncertainty_setup (clock skew and clock jitter and) coming, dc to check the advance setup time clk_uncertainty_setup meets
# Uncertainty of clock
set clk_latency [exprclk_period / 200]; # Set the clock uncertainty, just to set the relative uncertainty for the establishment of the time, is likely to advance the rising edge of the clock clk_uncertainty_setup (clock skew and clock jitter and) coming, dc advance clk_uncertainty_setup check setup time of clock Uncertainty meets sET clk_latency # [exprclk_period / 10];
# set clock delay, the clock is a clock signal from the origin to the actual transmission time point of the design defined in clock
# latency of the Network clock
# considered reg1 + combo1 -------- combo2_input + reg2 combo2_output ----------- combo3 + reg3 model to explain input_delay + and output_delay, intermediate combo2_input + reg2 + combo2_output integrated module to
set input_delay [ clk_period expr /. 4];
# delay setting input, an external input is provided (combinational logic Combo1) how much time (i.e., from rising edge of the clock input to the delay experienced by data arrives), DC calculates how much time is left inside the combined
logic combo2_input, for example, the clock period is 10ns, input_delay is 4ns, then there are (6-tsu) left Internal combinational logic
combo2_input
# Delay of the Input Clock All the except the ports INPUT
set output_delay [exprclk_period / 4]; # delay setting input, an external input is provided (combinational logic Combo1) how much time (i.e., from rising edge of the clock input to the delay experienced by data arrives), DC calculates how much time is left inside a combinational logic combo2_input, for example, the clock period is 10ns, input_delay is 4ns, then there are (6-tsu) leaving the internal combinational logic delay of the Input # All combo2_input the ports the except clock sET INPUT output_delay [exprclk_period /. 4];
# set the output delay, provided with an external output (the combinatorial logic combo3) how much time (i.e., the external combinational logic delay), dc is calculated how much time left internal combinational logic combo2_output, for example, the clock period is 10ns, output_delay as 4ns, then there are (6- Tclk2Q) leaving the internal combinational logic combo2_output
# Output All the ports of the Output Delay
sET area_desired 0;
expectation # installation area for set_max_area
sET wire_load_model "smic18_wl20";
# in order to precisely calculate the load line disposed model (DC supports three modes:
in order to decide how to select for cross-border level Line load line model) for calculating the delay timing path for set_wire_load_model
# NET the Model of Intra The
SET output_load "Typical / NAND2BX1 / the AN";
# In order to precisely calculate the output time of the circuit is necessary to provide a load port (input or output load external capacitor), for all output ports is designated a load, when the integrated dc will think there is such a load (not to say Integrated when forced to add here a capacitor), when DC integrated device will be selected to meet this load, for example, assume an output port has been known to be driven is an inverter, the output load of the inverter is set to this load input can, of course, may be arranged large, so a large dc will drive capability of the device to meet all the unit is driven. This effect is command information back annotation Butuhouti capacitor module taken on the output port is provided in the integrated process of FIG front cloth and to connect the capacitive load, a selected load as the output load of a device where pins , which is considered dc output ports to reach all can drive this pin
# at the output_load Model of
the SET synthesis_reports {/ Home / chanshi / dc / report};
# designated comprehensive report output directory
#name of report directory
sh mkdir synthesisreports;settimingreport"synthesisreports;settimingreport"synthesis_reports/activedesign_timing.rpt"settimingmax20report"activedesign_timing.rpt"settimingmax20report"synthesis_reports/activedesign_timingmax20.rpt"setareareport"activedesign_timingmax20.rpt"setareareport"synthesis_reports/activedesign_area.rpt"setreferencesreport"activedesign_area.rpt"setreferencesreport"synthesis_reports/activedesign_references.rpt"setcellreport"activedesign_references.rpt"setcellreport"synthesis_reports/activedesign_cell.rpt"setconstraintreport"activedesign_cell.rpt"setconstraintreport"synthesis_reports/activedesign_constraint.rpt"setpowerreport"activedesign_constraint.rpt"setpowerreport"synthesis_reports/activedesign_power.rpt"setchecksyntaxreport"activedesign_power.rpt"setchecksyntaxreport"synthesis_reports/active_design\_check_design.rpt"
{synthesis_netlist SET / Home / chanshi / dc / Result};
# specify netlist and sdf / sdc / db directory file output, the present generation is not supported db dc file
to the #NAME outfile Directory of
SH mkdiractive_design \ _check_design.rpt "SET synthesis_netlist {/ home / chanshi / dc / result} ; # specify netlist and sdf / sdc / db output directory file, this file db dc does not support the generation of outfile directory SH mkdirsynthesis_netlist to the #NAME;
# Create a directory
set out_netlist "synthesisnetlist / synthesisnetlist / active_design . V ";
SET out_db" synthesisnetlist / synthesisnetlist / active_design.db ";
SET out_sdf" synthesisnetlist / synthesisnetlist / active_design.sdf ";
SET out_sdc" synthesisnetlist / synthesisnetlist / active_design.sdc ";
# ------------------------------------------------- ----
# the Step 4:
# DC Memory to the Read Design
# ----------------------------------- ------------------
foreach active_files files read_verilog $ active_files} {
# foreach statement, files {read_verilog $ active_files} #foreach statement, files a file list, the list of assigned to each file in turn active_files, then perform read_verilog function active_files, read_verilog equivalent function performed in turn for each file
#exit
current_design $ active_design
# sets the current design
link
unit links # instantiating the design reference current to the current design (i.e. read link_library specified library to the current design)
uniquify
# of starting each instance of the name of a single unit (for the case where multiple references to a module)
#check_design > check_syntax_report
#if {[check_design] == 0} {
# echo "Check Design Error!";
# exit;
# }
#-----------------------------------------------------
# Step 5 :
# Constraint
#-----------------------------------------------------
#-----Net load------
set_wire_load_model -namecheck_syntax_report #if {[check_design] == 0} { # echo "Check Design Error!"; # exit; # } #----------------------------------------------------- # Step 5 : # Constraint #----------------------------------------------------- #-----Net load------ set_wire_load_model -namewire_load_model
#设置线载模型
set_wire_load_mode top
# Set the line load mode (top: at all levels and in all connections will inherit the top module carrying the same line model, because the size of the largest top-level circuit, so the maximum connection delay line model carrying the most pessimistic; enclosed: Select the connection is located sub-carrier line model modules, sub-modules circuit scale smaller than the top layer, the connection delay is small; segmented: not used, to cross-level wiring boundary)
# ----- ------ Clock
create_clock clockname-period -name [exprclockname-period [exprclk_period] [get_ports clock_name]
# set clock
set_clock_uncertainty -setupclock_name] # set clock -setupclk_uncertainty_setup set_clock_uncertainty [get_clocks clock_name]
# set clock uncertainty
set_clock_latencyclock_name] # set clock uncertainty set_clock_latencyclk_latency [get_clocks clock_name]
# set clock delay
set_dont_touch_network [get_clocksclock_name] # set clock delay set_dont_touch_network [get_clocksclock_name]
# In the optimization process of the clock network does not change and replacement reasons: due to the large load clock port, DC will use Buffer to increase their driving ability. But generally designers use layout tools to accomplish this work, it is necessary to indicate DC do not modify the clock network, you can select the image above "Do not touch network" set.
set_dont_touch_network [get_ports reset_name]
# of the reset signal is not changed and replaced in the optimization process
set_ideal_network [get_portsreset_name] # of the reset signal is not changed and replaced set_ideal_network [get_portsreset_name] During optimization
# of reset arranged over the net, because reset the fanout too, are arranged over the wire web former general layout, specific reasons to be studied Drive ------ ----- #
#set_driving_cell -lib_cell xr02d2 -pin -library CSM35OS142_typ A1 [all_inputs]
set_driving_cell -lib_cell -pin the Y NAND2BX1 [all_inputs]
# for all input ports (to remove the clock and reset) disposed drive model, drive strength, and thereby specifying the conversion time
set_drive 0 [get_ports clock_name]
# driving capability of the clock is set to infinity, i.e. its resistance to 0
set_drive 0 [get_portsclock_name] # clock drive capability is set to infinity, is about to set its impedance 0 set_drive 0 [get_portsreset_name]
# Above
# ----- INPUT / Output Delay ------
SET allin_except_CLK [remove_from_collection [all_inputs] [get_ports CLK]]
set_input_delay [expr inputdelay] -clockinputdelay] -clockclock_name allin_except_CLK
# Set input delay
set_output_delay [exprallin_except_CLK # set input delay set_output_delay [exproutput_delay]-clock clock_name [all_outputs]
# output delay set
# ------ ----- the output Load
set_load [load_ofclock_name [all_outputs] # # set output delay ----- load ------ set_load the output [load_ofoutput_load] [all_outputs]
# set load all output ports
# ------ ----- Area
#set_max_area area_desired
# ----- INSERT ASSIGN Replace Buffer - ----
set_fix_multiple_port_nets -all -buffer_constants
# If a wire mesh connected to multiple ports will appear in the netlist assign statement, this is a mistake, in order to avoid such errors, to eliminate multi-port connection, can be eliminated by inserting a buffer (See in particular " ASIC design practical tutorial "P146)
# ---------------------------------------- -------------
# the Step 6:
# the Compile
# Also CAN use compile_ultra
# ------------------------- ----------------------------
the compile -map_effort Medium -boundary_optimization
#compile -map_effort Medium
# -boundary_optimization -area_effort High
#compile -incremental_mapping
# -------------------------------------------------- ---
# the Step 7:
# Reports (the Timing, Area ...)
# -------------------------------- ---------------------
remove_unconnected_ports [get_cells -hier {*}]
change_names -hierarchy -rules TAN_RULE
report_timing -delay max -max_paths 1> area_desired # ----- insert buffer replace assign ------ set_fix_multiple_port_nets -all -buffer_constants # If a plurality of ports connected to the line network, the network will assign statement table this is a mistake, in order to avoid such errors, to eliminate multi-port connection, can be eliminated by inserting a buffer (see in particular "specific integrated circuit design practical tutorial" p146) # ---------- ------------------------------------------- # Step 6: # Compile # Also can use compile_ultra # --------------------------------------------- -------- compile -map_effort medium -boundary_optimization #compile -map_effort medium # -boundary_optimization -area_effort high #compile -incremental_mapping # -------------------- --------------------------------- # Step 7: # Reports (Timing, Area ...) # - -------------------------------------------------- - remove_unconnected_ports [get_cells -hier {*}] change_names -hierarchy -rules TAN_RULE report_timing -delay max -max_paths 1>timing_report
report_timing -delay max -path end -max_path 80 > timingmax20reportreportarea>timingmax20reportreportarea>area_report
report_reference > referencesreportreportcell[getcells−hier∗]>referencesreportreportcell[getcells−hier∗]>cell_report
report_constraint -all_violators -verbose > constraintreportreportpower−analysisefforthigh−verbose>constraintreportreportpower−analysisefforthigh−verbose>power_report
check_design > check_syntax_report
#-----------------------------------------------------
# Step 8 :
# Write Files (netlist out)
#-----------------------------------------------------
change_names -rule verilog –hier
write -format verilog -hierarchy -outputcheck_syntax_report #----------------------------------------------------- # Step 8 : # Write Files (netlist out) #----------------------------------------------------- change_names -rule verilog –hier write -format verilog -hierarchy -outputout_netlist
write -format db -hierarchy -output outdbwritesdfoutdbwritesdfout_sdf
write_sdc $out_sdc
exit
#----------------------end-------------------
------------
Reproduced
