Understanding of ASIC DC Synthesis
DC synthesis process
Input design file + specified process library file + constraint file
After DC synthesis, output gate-level netlist and synthesis report that meet expectations
input and output data
Input file: design file (verilog, etc.), process library (db)
Output file: netlist (Netlist), report
DC's understanding of input data
design object
The DC analyzes the read design and divides it into different design objects.
DC divides design objects into eight different types:
Design
(Cell)
Reference (Reference)
Port (Port)
Wiring (Net)
Clock (Clock)
Library (Library)
craft library
The craft library includes the following information:
Library class
Library-level property
Environment description- Scale Factor
- working conditions
- Timing Range Model
wire model
unit description
It can be seen that the synthesis of DC is to convert the design to the gate-level netlist corresponding to the process library according to the input constraint file
Constraints and Optimizations
Model the design working environment according to the actual situation, including PVT (process/voltage/temperature), clk, delay, drive, load and other working environments
excerpt
DC synthesis is based on paths, and each path has Cell and Net, so path-based synthesis is to calculate delay and rc on the path (dc is estimated using the interconnect wire load model)
DC synthesis is based on paths, and each path has Cell and Net, and the Cell delay is obtained according to input_transition and out_load, and the Net delay is obtained according to fanout_length, resistance, capacity.
The constraints in DC are actually designing an environment for the Chip, such as driving the input port Cell of the Chip, or which cells or loads connected to the ports are driven by the output port of the Chip, as well as the process, voltage, and temperature of the chip.
References
[1]. Design Compiler manual
[2]. EETOP information