SDRAM Controller Operation Timing

This is a study note organized by http://dengkanwen.com/137.html , invade and delete!

How SDRAM works

Internal state jump diagram

A few places we need to focus on:

1) The thick black line indicates that it will automatically jump to another state in this state, and the thin black line indicates that the command needs to be given to jump.

2) A few places we focus on:

From IDLE state to WRITE state:
​ 1) In IDLE state, you need to activate a row for the ACT command first, and it is in the Row Active state;
​ 2) After the Row Active state, giving the Write command will enter the WRITE state;
​ 3) In After the WRITE state, give the Write command again to continue writing data.
WRITE state to IDLE state:
​ 1) Give the PRE command in the WRITE state, the SDRAM will jump out of the WRITE state and enter the Precharge state;
​ 2) After the Precharge state, it will automatically enter the IDLE state.

​ One reason to jump from the WRITE state to the IDLE state is that we need to perform a refresh operation, and to enter
the refresh operation, we must enter from the IDLE state.
​ Another point, some friends may have seen that there is a WRITEA state under the WRITE state,
indeed , but carefully, have you noticed that when it is in the WRITEA state, it will automatically enter the Precharge state. That is to say, the work efficiency of WRITEA is much lower than that in WRITE state, so in some scenarios where data interaction is faster, we use WRITE state. In this set of tutorials, we also only talk about the WRITE state. The speed can be done, and the slow operation is not a problem.

SDRAM initialization module

First look at the initialization sequence diagram given by the official data sheet

initialization process

1) First, there is a delay of 200us (corresponding to T in the lower left of the figure),

2) After the delay is satisfied, give a Precharge command, and specify A10 and Bank address at the same time ; (If A10 is high (All Banks), it means that all Banks are precharged, and the Bank address is not required at this time. , if A10 is low (SINGLE BANK), you need to specify the address of a bank. Generally high)

3) Then after the "tRP" time, give the "AutoRefresh" command, then after the "tRC" time, and then give the "Auto Refresh" command , (you do not need to specify the bank address (please pay attention to the instructions in the lower right corner, We don't need to care about the data in the gray part ).

4) Then the mode register setting is performed after the time of "tRP". When setting the mode register, the instructions that need to be given will be a little more complicated. The manual shows that A0~A11 and BA0, BA1 are used, let's see how the mode register should be set, as shown in the figure:

​ Here is an explanation of burst read and write: the burst length (A2~A0) is set to 4. When we write, the data is written every 4 pieces of data, that is to say, if we give a write command, it will send SDRAM writes 4 data, and the four addresses are consecutive (if the burst type is set to be non-consecutive, the addresses will not be consecutive, we need to write a data to the address once, which consumes more memory)

Several problems in the initialization sequence diagram

1) What is the time of tRC, tRP, tMRD, and how many clock cycles?

Refer to the AC ELECTRICAL CHARACTERISTICS section in the official data sheet ML0006 0012-2 given

tRC：63ns

tRP：20ns

tMRD：2cycle

If the fpga internal frequency is 50MHZ, it is exactly 20ns. (4clk, 1clk)

2) How to set the parameters of several command commands in the sequence diagram

The above is the entire initialization process. We finally use the sequence diagram drawn by Kevin as a summary.

The specific code is sdram_init;

SDRAM refresh module

Let's take a look at the refresh timing diagram given by the official data sheet first.

The timing diagram analysis of the refresh operation is similar to the previous one.

Several problems in the refresh sequence diagram

1) How long is the interval between two refreshes?

​ The maximum time for SDRAM internal capacitors to store data is 64ms, and our BANK has 4096 lines, 64ms/4096～=15us, which means that in order to ensure that the data inside SDRAM is not lost, the maximum time interval between two refreshes It is 15us, so in order to allow more time for SDRAM to read or write, we set the SDRAM refresh cycle to 15us. (If the system clock is 50MHZ, it counts as 750)

​ Each time SDRAM is refreshed, it operates on each row, not charging each capacitor separately, so every time a refresh is performed, the capacitors in the row are charged, we can understand that it happens synchronously

2) In each automatic refresh, we need to give a "Precharge" command, what does this command do?

You can look at the state diagram at the beginning. If the SDRAM is in the "WRITE" or "READ" state at this time, this "Precharge" command can make the SDRAM jump out of the "WRITE" or "READ" state and enter the "IDLE" state. . Next, after the "tRP" time, give an "Auto-Refresh" command to enter the refresh state.

But the Precharge command at this time is given in the write status module. The Precharge command is not required in the refresh module.

SDRAM Arbitration Module

Before introducing the arbitration module, let's consider a question:

​ If I am letting the SDRAM write data, is it time for the SDRAM to refresh, do I have to let the SDRAM perform the refresh operation immediately? This is definitely not realistic, and the remaining data that has not been written will inevitably be lost. We can't let our data be lost, and we must ensure that the SDRAM is refreshed to ensure that the data in the corresponding bank of our entire SDRAM is not lost. How should we write the code?

We can consider doing this: if the refresh time is up, let the write operation finish writing the 4 data being written (burst length is 4), and then perform the refresh operation. And if the read operation also encounters a situation that needs to be refreshed, we can also do the same, let the data read first, and then perform the refresh operation.

In order to solve the situation of inconvenient control between various modules, we introduce a new mechanism - "arbitration" mechanism. What is "arbitration" used for? Here, "arbitration" is equivalent to the boss of our SDRAM controller, and the various operations of SDRAM are coordinated uniformly: reading, writing and automatic refresh are all controlled by "arbitration".

Arbitration module state machine diagram:

Wiring between the arbitration module and other modules:

Note: Be sure to clarify whether you are talking about the connection between modules or the jump between state machines.

Arbitration Module Analysis

1) After the initialization operation is completed, it enters the "ARBIT" arbitration state. Only when it is in the arbitration state, the "Arbitration Boss" can issue commands.

2) When the state machine is in the "WRITE" write state, if the time to refresh the SDRAM is up, the refresh module sends a refresh request ref_req signal to the write module and the arbitration module at the same time.

3) When the writing module receives ref_req, after the writing module finishes writing the current 4 data (burst length is 4), the writing end flag flag_wr_end of the writing module is pulled high, and then the state machine enters the "ARBIT" arbitration state.

4) After being in the arbitration state, there is a refresh request ref_req at this time, then the state machine jumps to the "AREF" state and the arbitration module sends the ref_en refresh enable, the refresh module pulls the refresh request signal ref_req low and sends a refresh command to the sdram.

5) After the refresh is completed, the refresh module sends the flag_ref_end refresh end flag to the arbitration module, and the state machine jumps to the "ARBIT" arbitration state.

Note that after refreshing and jumping to the "ARBIT" arbitration state, if all our data has not been written before (Kevin refers to all data, not 4 data of a burst length), then at this time We still have to write the request "wr_req" to the arbitration module, and then after a series of judgments by the arbitration module, if it meets the timing of the write operation, then give the write module a write enable signal "wr_en", and then jump to "WRITE" to write state and the writer starts working.

SDRAM Writer

The write operation timing diagram given by the official data sheet

The analysis of the sequence diagram can refer to the analysis of the previous initialization process.

Now let's consider another question: Suppose we need to write two lines of data to SDRAM now, when can we exit the write state of the arbitration state machine:
1) The data has been written ; if we want to write again, we need an external The Wr_trig triggers
2) SDRAM needs to be refreshed ; there is a refresh request signal externally, and the data has been written this time; go to the external arbitration module to perform the refresh operation, if the refresh is completed and need to continue to write, write module request, the arbitration module makes can.
3) The data has not been written, and the next line needs to be activated to continue writing . After writing the mark in this line, re-enter the act command to write the next line

We turn these three states into a state machine. as the picture shows:

Note that the IDLE state in the figure above is not to be confused with the IDLE state in the previous initialization. This IDLE is the initialization part of the state machine in the writing module.

S_WR:
        if(wr_data_end == 1'b1)                       
                state   <=      S_PRE;                 
        else if(ref_req == 1'b1 && burst_cnt_t == 'd2 && flag_wr == 1'b1)       
                state   <=      S_PRE;                 
        else if(sd_row_end == 1'b1 && flag_wr == 1'b1)
                state   <=      S_PRE;
S_PRE:
        if(ref_req == 1'b1 && flag_wr == 1'b1)         
                state   <=      S_REQ;
        else if(flag_pre_end == 1'b1 && flag_wr == 1'b1) 
                state   <=      S_ACT;
        else if(flag_wr == 1'b0)                       
                state   <=      S_IDLE;  

We draw the writing module timing diagram from the above:

Analyze the five state machines in the writer:

1) IDLE: The external Wr_trig triggers the write signal and enters the S_REQ state. The writing module pulls Flag_wr high until the data is completely written.

2) S_REQ: The Flag_wr signal is pulled high, and the S_REQ state sends a request write signal wr_req to the external arbitration. The external arbitration module judges that the writing operation can be performed and sends the wr_en enable signal to the writing module, telling the writing module to start writing. Enter the S_ACT state.

3) S_ACT: The writing module is in the S_ACT state, issues an ACT command (command), and specifies the row address of the bank . The end of the ACT command issues the Flag_act_end end flag. Enter the S_WR state.

4) S_WR: issue a write command to start writing data, at this time you need to specify the column address

After a row of data is written, the Sd_row_end flag signal is issued. When a refresh request occurs, the Flag_wr_end flag signal is sent out after the group of data is written. After all data is written, the Wr_data_end signal flag is returned.

5) S_PRE: Precharge command, enter the precharge state, and return to the Flag_pre_end flag signal after charging.

SDRAM read module

The SDRAM read module is the same as the write module and will not be described in detail here.

Read module timing diagram:

There is one problem to be aware of:

After we give the read command again, the data is given with a delay of two cycles. This time period is called the latency CAS.

Code writing skills:

1) Write the main state machine first

2) Define the timing signal flags used in the timing diagram;

reg                             flag_wr       ;
reg     [ 4:0]                  state         ;
//-----------------------------------------------
reg                             flag_act_end  ;
reg                             flag_pre_end  ;
reg                             sd_row_end    ;
reg     [ 1:0]                  burst_cnt     ; 
reg     [ 1:0]                  burst_cnt_t   ; 
reg                             wr_data_end   ;
//-----------------------------------------------
reg     [ 3:0]                  act_cnt       ;
reg     [ 3:0]                  break_cnt     ;
reg     [ 6:0]                  col_cnt       ;
//-----------------------------------------------
reg     [11:0]                  row_addr      ;
wire    [ 8:0]                  col_addr      ;

3) Then write the code generated by each flag signal according to this table