1. The principle of Uart serial port

1. Introduction to serial communication protocol

Serial interface is abbreviated as serial port, also called serial communication interface or serial communication interface (usually referred to as COM interface), which is an extended interface using serial communication. Serial Interface refers to the sequential transmission of data bit by bit. Its characteristic is that the communication line is simple, as long as a pair of transmission lines can achieve two-way communication (the telephone line can be directly used as the transmission line), which greatly reduces the cost, and is especially suitable for long-distance communication, but the transmission speed is slow.

The serial interface can be divided into synchronous serial interface (English: SynchronousSerialInterface, SSI) and asynchronous serial (UART, universal asynchronous receiver transmitter) from the transmission mode. The synchronous serial interface is a commonly used industrial communication interface. UART is a chip whose parallel input becomes serial output, usually integrated on the motherboard. UART includes a TTL level serial port and an RS232 level serial port. TTL level is 3.3V, while RS232 is negative logic level. It defines +5~+12V as low level and -12~-5V as high level. This experiment uses a serial interface from USB to TTL.

The serial interface includes RS-232-C, RS-422, RS485, etc. according to electrical standards and protocols. The RS-232-C, RS-422 and RS-485 standards only specify the electrical characteristics of the interface, and do not involve connectors, cables or protocols.

In computer science, most complex problems can be simplified by layering. For example, the chip is divided into the kernel layer and on-chip peripherals; the STM32 standard library is the software layer between the registers and the user code. For the communication protocol, we also understand it in a layered manner. The most basic is to divide it into a physical layer and a protocol layer. The physical layer stipulates that the communication system has the characteristics of mechanical and electronic functions to ensure the transmission of the original data on the physical media. The protocol layer mainly stipulates the communication logic, and unifies the data packing and unpacking standards of the sending and receiving parties. To put it simply, the physical layer stipulates that we communicate with our mouth or the body, while the protocol layer stipulates that we communicate in Chinese or English.

2. The physical layer and protocol layer of the serial port

2.1 Physical layer

There are many standards and variants of the physical layer of serial communication. We mainly explain the USB to serial communication protocol. The USB port signal level can be converted to TTL level by using the USB to TTL chip CH340g. For other controllers, we use the controller as FPGA. Its block diagram is as follows:

Figure 1: USB to serial structure diagram

The 5VTTL level standard is: Logic 1 is 2.4V-5V, and Logic 0 is 0V-0.5V.

Figure 2: USB to UART serial port circuit

The picture shows the USB to UART serial port circuit, which is connected to the D+ and D- interfaces of CH340 through the D+ and D- two data lines of USB, and converts the data into TTL level signals through the two signal lines TXD and RXD of CH340 Send and receive data with FPGA.

2.2 Protocol layer

The data packet of serial communication is transmitted by the sending device to the RXD interface of the receiving device through its own TXD interface. In the protocol layer of serial communication, the content of the data packet is specified. It is composed of start bit, body data, check bit and stop bit. The data packet format of both parties must be agreed upon in order to send and receive data normally. The composition is shown below Picture:

2.2.1. Baud rate

This chapter mainly explains serial asynchronous communication. In asynchronous communication, there is no clock signal. Therefore, the two communication devices need to agree on the baud rate, that is, the length of each symbol, in order to decode the signal, as shown in Figure 206. Each grid separated by the dotted line represents a symbol. Common baud rates are 4800, 9600, 115200, etc.

2.2.2. Start and stop signals of communication

A data packet of serial communication starts from the start signal until the end of the stop signal. The start signal of the data packet is represented by a logic 0 data bit, and the stop signal of the data packet can be represented by 0.5, 1, 1.5 or 2 logic 1 data bits, as long as the two parties agree to agree.

2.2.3. Valid data

Immediately after the start bit of the data packet is the content of the main data to be transmitted, also known as valid data. The length of valid data is often agreed to be 5, 6, 7 or 8 bits long.

2.2.4. Data verification

After the valid data, there is an optional data check bit. Because data communication is relatively more susceptible to external interference, which results in deviations in transmission data, you can add check bits during the transmission process to solve this problem. The verification methods include odd, even, space, mark, and noparity. They are introduced as follows:

Odd parity requires an odd number of valid data and "1" in the parity bit. For example, an 8-bit valid data is 01101001. At this time, there are a total of 4 "1"s. To achieve the odd parity effect, check The check bit is "1", and the last transmitted data will be 8 bits of valid data plus 1 bit of check bit for a total of 9 bits.
Even parity and odd parity requirements are just the opposite. The number of "1"s in the frame data and parity bit is required to be an even number, such as data frame: 11001010, at this time the number of "1" in the data frame is 4, so even The check digit is "0".
0 check means that no matter what the content of the valid data is, the check bit is always "0", and 1 check means the check bit is always "1".
In the case of no check, no check bit is included in the data packet.

2. Experimental platform

After understanding the basic principle and transmission protocol of serial communication, the communication function is realized through the USB serial port of the PC and FPGA. The following figure shows the connection example of the USB to TTL circuit and Cyclone IV E FPGA:

Figure 3: USB to TTL circuit and Cyclone IV E FPGA connection example

The following table is the FPGA and UART pin allocation table:

Table 1: UART pin allocation table
Siginal Name	FPGA Pin
UART_RX	PIN_B5
UART_TX	PIN_A6

3. Experimental requirements

The development board AC620 of Xiaomei is used. The three buttons S0, S1, S2 are in idle state when S0 is pressed, and serial communication is not performed in this state; when S1 is pressed, it is in state 1: PC sends data to FPGA, Data is sent by PC serial port, FPGA receives 8 bits of data, select whether the 8 LEDs in the corresponding position are bright or dark; S2 is in state 2: FPGA sends data to PC, FPGA sends a data 8'hff cyclically, PC serial port receive.

Tip: Since there are only 4 LEDs on the development board from LED0~LED3, 8 of them are needed in this design. Therefore, the signal indicators connected to the two TXD and RXD interfaces of RS232 and CAN communication are used as the LEDs we need.

Figure 4: LED location diagram used on the board

FPGA USB serial communication (1)