Table of contents

1. Digital tube static display

The digital tube of FPGA has 4 bits and 8 segments . ( Bit and segment are common positive, that is, low level is active )

The 4 bits selected by the bit (binary): respectively the 1st, 2nd, 3rd, and 4th digital tubes.

The 8 bits (binary) of the segment selection: respectively for the h, g, f, e, d, c, b, a segments.

The following uses 4-digit (all) digital tubes to display the number "1":

//数码管（共阳：低电平有效）
//FPGA的数码管：段选和位选都共阳
module my_and(dig, seg);

output wire [3:0] dig;		//位选（选定某一个数码管）
output wire [7:0] seg;	//段选（选定一个数码管上的小段）

assign dig = 4'b0000;	//位选（0000：4个零，共4个数码管，全选）

assign seg = 8'b1111_1001;	//段选（第6、7段为0，显示的是“1”）

endmodule

Two, digital tube dynamic display

Since different numbers need to be displayed, the digital tubes of the FPGA cannot be operated individually, but can only be operated in groups.
So you can only give each digital tube a different frequency, and then display it in turn.
Note: The frequency should be appropriate here:
too fast frequency: aliasing is easy to occur;
too slow frequency, slow change, obvious flow display.

Frequency is too slow (pipeline change):

Frequency too fast (aliasing):

Normal frequency:

1. Variable definition

module my_and(dig, seg, clk, rst_n);

input clk, rst_n;
output reg [7:0] seg;		//段选（选定一个数码管上的小段）
output reg [3:0] dig;		//位选（选定某一个数码管）

reg [25:0] cnt;
reg [1:0] wei;

2. Timing (60us)

Time to 60us, so that the bit changes once .

//定时（60us变化位变化一次）
always@ (posedge clk, negedge rst_n)
begin 
	//按下复位键（清空）
	if(!rst_n)		
		cnt <= 1'b0;		//清空
	
	else if(cnt != 12'd3000)	//60us(3000*20ns=60us)
		cnt <= cnt + 1'b1;//加1
	
	else
	begin
		cnt <= 1'b0;		//清空
		wei <= wei + 1;	//位+1
	end
end

3. Dynamic display

Here the bit (dig) and the segment (seg) are changed, and the segment changes with the bit.

//动态显示
always@(*)
begin 
	case(wei)
		//2
		2'b00: 
		begin
			dig <= 4'b0111;
			seg <= 8'b1010_0100;
		end
		//5
		2'b01:
		begin
			dig <= 4'b1011;
			seg <= 8'b1001_0010;
		end
		//0
		2'b10:
		begin
			dig <= 4'b1101;
			seg <= 8'b1100_0000;
		end
		//8
		2'b11:
		begin
			dig <= 4'b1110;
			seg <= 8'b1000_0000;
		end
	endcase
end

the code

//数码管动态显示（共阳：低电平有效）
//由于要显示不同的数字，但是FPGA的数码管没办法单独操作，只能群操作。
//所以只能给每个数码管不同的频率，然后依次显示
//注：这里频率要给适当，
//频率过快：容易发生混叠；
//频率过慢，变化慢，明显的流水式显示
/*对照表
4'h0 : seg = 8'hc0; //显示"0"
4'h1 : seg = 8'hf9; //显示"1"
4'h2 : seg = 8'ha4; //显示"2"
4'h3 : seg = 8'hb0; //显示"3"
4'h4 : seg = 8'h99; //显示"4"
4'h5 : seg = 8'h92; //显示"5"
4'h6 : seg = 8'h82; //显示"6"
4'h7 : seg = 8'hf8; //显示"7"
4'h8 : seg = 8'h80; //显示"8"
4'h9 : seg = 8'h90; //显示"9"
4'ha : seg = 8'h88; //显示"a"
4'hb : seg = 8'h83; //显示"b"
4'hc : seg = 8'hc6; //显示"c"
4'hd : seg = 8'ha1; //显示"d"
4'he : seg = 8'h86; //显示"e"
4'hf : seg = 8'h8e; //显示"f"
*/
module my_and(dig, seg, clk, rst_n);

input clk, rst_n;
output reg [7:0] seg;		//段选（选定一个数码管上的小段）
output reg [3:0] dig;		//位选（选定某一个数码管）

reg [25:0] cnt;
reg [1:0] wei;


//定时（60us变化位变化一次）
always@ (posedge clk, negedge rst_n)
begin 
	//按下复位键（清空）
	if(!rst_n)		
		cnt <= 1'b0;		//清空
	
	else if(cnt != 12'd3000)	//60us(3000*20ns=60us)
		cnt <= cnt + 1'b1;//加1
	
	else
	begin
		cnt <= 1'b0;		//清空
		wei <= wei + 1;	//位+1
	end
end


//动态显示
always@(*)
begin 
	case(wei)
		//2
		2'b00: 
		begin
			dig <= 4'b0111;
			seg <= 8'b1010_0100;
		end
		//5
		2'b01:
		begin
			dig <= 4'b1011;
			seg <= 8'b1001_0010;
		end
		//0
		2'b10:
		begin
			dig <= 4'b1101;
			seg <= 8'b1100_0000;
		end
		//8
		2'b11:
		begin
			dig <= 4'b1110;
			seg <= 8'b1000_0000;
		end
	endcase
end

endmodule

Static display and dynamic display of FPGA (5) digital tube