1 Introduction
DDR is called the Double Data Rate SDRAM, which is double the rate SDRAM, SDRAM data once in a transmission cycle CLK, and a cycle of CLK DDR data is transmitted twice, once at the rising edge and falling edge, respectively, of each transmission, the the concept is called prefetching, the general use of MT / s units when describing DDR speed, which is how many megabytes of data transfers per second.
2, DDR block diagram
Micro DDR3L the chip will next be described MT41K256M16 block diagram of the chip is a DDR3L 512MB of memory chips, a block diagram is shown below:
Next, each reference frame of FIG simple description given above:
(1) a control line
ODT: on-chip enable terminal, ODT enable the terminal resistor and the chip is prohibited;
ZQ: output drive external reference calibrated pin to be an external resistor RZQ VSSQ, generally to ground;
RESET: reset pin chip, active low;
CKE: Clock enable pin;
A12: A12 for the address pins, also known as BC-pin, there is another function, A12 will be sampled during the READ and WRITE command to decide whether to burst chop is executed;
CK, CK #: clock signal line, a clock line DDR3 differential clock line, the control signals and address signals are collected at the rising edge of CK and CK # falling edge at the intersection of;
CS #: chip select signal, active low;
RAS #: row address strobe signal;
CAS #: column address strobe signal;
WE #: write enable signal.
(2) address lines
A[14:0]：
(3) Bank select line
BA [2: 0]:
(4) Bank region
(5) data line
DQ[15:0]：
(6) data strobe pins
LDQS,LDQS#：
UDQS,UDQS#：
(7) Data input mask pins
LDM/UDM：