DDR specifications:
DDR state diagram:
DDR refresh Description:
Electrical characteristics:
Work Mode Introduction:
1.1 self-refresh mode (Self Refresh Mode)
In self-refresh supermarket DDR4 SDRAM to store data in the memory array, even when the other part of the system have been powered off, still retains its function. There is an internal counter to adjust a DRAM self-refresh operation. SRE before executing the command, in all Bank DRAM must be in the IDLE state, the need to perform PRE ALL command. SRE is defined in command at the rising edge of the clock, CS_n, RAS_n / A16, CAS_n / A15 and CKE maintains a low level, WE_n / A14 and ACT_n remains high. Since there is refresh the data in SDRAM is naturally hold of . After entering the SDRAM self refresh, SDRAM controller will disable the Clock output to the SDRAM, thus reducing the overall power consumption is down to this mode comprises an automatic mechanism for the self-refresh, a DRAM contains a temperature sensor, a sensor according to this data, automatically selects refresh command cycle interval.
1.2 power down mode (Power Down Mode)
In the case of CKE is low, or send a NOP INHIBIT command allows SDRAM to enter the power down mode. Power Down There are two mode, called PRECHARGE POWER-DOWN, another is called ACTIVE POWER-DOWN. If you enter Power down mode in all the bank are under idle state (no open line), then this mode is called PRECHARGE POWER-DOWN (power of the state is about 300uA). If you enter Power down mode in case there is open line (active row) next, then this mode is called ACTIVE POWER-DOWN (power of the state is about 6mA). SDRAM chip want to exit power down mode when CKE signal to be pulled, or send a NOP INHIBIT command allows SDRAM to exit power down mode. In order to further reduce power consumption, the SDRAM controller may disable the clock output off (at this time CKE is disable, even SDRAM controller generates a clock signal, SDRAM internal logic circuit is not driven). Everything looks very beautiful, the question is, whether the data can be maintained? Unfortunately, more than the Refresh period (tREF), data in SDRAM will not be maintained . Therefore, in order to save the data, we can make SDRAM controller to exit the power down mode when the auto refresh timer times out, the refresh operation is completed, after which, if there is no pending data, continue to enter the power down mode.
DDR4 DRAM provides a much lower power consumption Maximum Power Down mode. This mode is entered by configuring MR4.A4 = 1. , Deep Power Down. SDRAM Controller commands transmitted Deep Power Down SDRAM chips may be pushed to a low power state (approximately 15uA). This time the storage array power will be shutdown, which is means that all data is lost out this time, mode register set is maintained. When the user exits from the Deep Power Down, the need for a complete chip SDRAM initialization process.
DETAILED difference 2
2.1 saved data
In the SR mode, it can not guarantee the correctness of the data. In PD mode, PD mode Ruoguo duration not greater than 9 * tREFI, the DRAM can guarantee data accuracy.
2.2 clock input
In the SR mode Precharge PD mode, the controller may be performed within a predetermined range of a timing clock frequency changes or off the clock.
2.3 entry method
SRE SR mode by entering the command, SRX command exits. In PD mode is DES command, the CKE signal low to the low level to access to the CKE signal high through the exit to the high level.
2.4 IO Buffer state
In the SR mode, all IO Buffer are open.
In PD mode, in addition to CK_t, CK_c, CKE and RESET_n the IO Buffer, all other IO Buffer is in a closed state.
2.5 powered state
Both models are powered in an active state.
3 power difference
SR mode Act PD mode Pre PD PD mode Max
1mA 6mA 300uA 15uA
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Author: hierro_sic
Source: CSDN
Original: https: //blog.csdn.net/hierro_zs/article/details/71158846
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