DDR literacy - depth discussion on the Prefetch and Burst
Posted on 2017/8/15 13:17:55 Reading (12692) Comments (1)
DDR learning for some time, read a lot of information (part of the company's training materials, dozens of Bowen, Micron's Datasheet, JESD79 specifications, etc.) during. But there is a problem, like a long time (a lot of information did not say so), it has considered thoroughly understand, so write an article to share with you.
If that is mainly about related content Prefetch and Burst discussed next.
1, Prefetch Introduction
First, a brief Prefetch technology. The so-called prefetch, is pre-loaded, which is made of DDR technology era. In the SDR, and not the technology, so the storage capacity of each cell is equal to the width of the DQ (IO chip data bits wide). [About what is cell (memory cell can take a look, my previous blog: http://blog.chinaaet.com/justlxy/p/5100051913 )]
After entering the DDR era, there is a prefetch technology, DDR is two prefetch (2-bit Prefetch) , some companies are aptly called 2-n Prefetch (n represents the chip-bit wide). DDR2 is a four prefetch ( 'bit-the Prefetch. 4) , and DDR3 DDR4 all eighth bit prefetch (8-bit Prefetch). The 8-bit Prefetch can cause the kernel to clock a quarter of DDR clock, which is the fundamental meaning Prefetch lies.
Additional information: another way of saying that chip-bit wide configuration mode (the Configuration ), the DDR3 era, generally x4, x8, x16.
DDR3 below to an example, below is a simple schematic view of a simple prefetch Read, Write can be seen as a reverse process.
When DDR3 is x8 Configuration, Cell capacity of a 8x8bits, i.e. 8 bytes. In other words, it can be written after the specified bank, row and col address to the address of the address (or read) 8 Bytes.
2, back to a simple question on how to calculate the capacity of DDR3 SDRAM
To a certain type of DDR3 SDRAM Mircon example:
Content-red areas as study case (8 bank, x8 of Configuration):
Calculated as a (wrong):
64K*8*1K*8（Row Addressing * Bank Addressing * Column Addressing * x8 Configuration）= 4Gb（512 Megx8）。
This calculation is wrong most of the material presented to mislead a lot of beginners. This calculation loud noise like a promising pair. However, a closer scrutiny it, they can be found, according to a calculation logic is considered the capacity of each Cell is 1bit * 8 (x8 Configuration), that is 8bit. This results we discussed in the first portion (a Cell capacity of 64bits, Configuration under x8) match.
Of course, in some ways, a calculation is correct, because the Column Address bits actually isolated and the corresponding prefetch. For example DDR3 8-bit Prefetch 3bits of the Column Address, DDR2 4-bit Prefetch corresponding to 2bits is a Column Address. If only directly in accordance with a calculation to calculate it, the contact person for the first time for the DDR, there are some difficulties to understand, and this is the reason I wrote this blog post is.
The following calculations are given correct manner, and why.
Calculated two (right):
64K*8*（1K/8）*8*8（Row Addressing * Bank Addressing * (Column Addressing / 8) * x8 Configuration * 8-bit Prefetch）= 4Gb（512 Megx8）。
Many people will ask, why should address the column address (Column Addressing) divided by 8 it? It seems calculated two look more reasonable. Next, let's take a look at the block diagram of DDR3 SDRAM (or in Mircon a certain model, for example):
Big picture may look less clear, here come a few close-up:
Yes! You read right! Column Address 10bit addressing capability of only 128! ! ! Just eight times worse (which is why we divided by 8 in Column Addressing calculated two will)!
So the question again, why Column Address addressing capacity of only 128 it? Moji, please continue to look:
In the figure, can be clearly found, Column Address 10bits only the column address decoder for 7bits! 0,1,2 column address and useless! ! !
So, the question again! ......
0,1,2 column address, which is used to 3bits what the function? Or Mircon designer residual brain, deliberately wasted three bits? Obviously not.
This table has the following specifications in JESD79-3:
Can be found, Column Address of A2, A1, A0 three functions are used to Burst Order, and A3 is also used Burst Type functions. Since general, we are used in sequential write mode (i.e. {A2, A1, A0} = {0,0,0}), so that at this time no direct impact on the value of A3.
So, the question again! ......
Burst what the hell is it? Let us look at the third part.
3, DDR in Burst Length
Burst Lengths, abbreviated BL, refers to the burst length, the burst mode refers to the same row in the adjacent memory cells continuously for data transmission, the number of consecutive transmissions involved memory cells (row) is the burst length (SDRAM) , the middle number of the DDR SDRAM discontinuous transmission cycle. The portion mentioned Burst Type Burst Order and Burst Length actually arranged on the write sequence.
[Note: do not understand the relevant noun can take a look, before I Bowen: http://blog.chinaaet.com/justlxy/p/5100051913 ]
In the era of DDR3 SDRAM, the internal configuration uses 8n prefetch (prefetch) to achieve high-speed reading and writing. This also leads to the DDR3 8 are generally Burst Length. Of course, there is provided Bursth ength 4 (BC4), refers to additional pen 4 is transmitted or not it is considered invalid.
In the era of DDR2, the internal configuration uses a 4n prefetch, Burst length 4 and 8 are two, for the BL = 8 read and write operations, the operation will appear twice 4n Prefetch.
The figure is a DDR3 SDRAM Command Truth Table JESD79-3 given specification. Can be seen, there are three basic read and write modes (Fixed BL8 or BC4, BC4 on the fly, BL8 on the fly). This part of the contents in my previous blog post has been mentioned, not described in detail here.
4. References
