Preface
Recently, I am learning DDR3/DDR4 related knowledge, and summarized some experience from it, I want to record it on CSDN. I read a lot of great gods' posts on CSDN before, which are quite helpful to my study. Now I also want to record my learning process, hoping to have technical exchanges with you great gods. This is also the first time I have written a technical article. Please correct me if there are any errors.
1. Introduction to SDRAM and structure of DDR3
SDRAM has gone through five generations since its development, namely: the first generation SDR SDRAM, the second generation DDR SDRAM, the third generation DDR2 SDRAM, the fourth generation DDR3 SDRAM, and the fifth generation DDR4 SDRAM.
SDRAM: (Synchronous Dynamic Random Access Memory, Synchronous Dynamic Random Access Memory), developed on the basis of DRAM, is a type of DRAM. Synchronization means that the memory work requires a synchronized clock, the transmission of internal commands and the transmission of data All are based on the clock; dynamic means that the storage array needs to be constantly refreshed to ensure that data is not lost; random means that data is not stored linearly in sequence, but data is read and written by a specified address.
Next, let's take a look at the internal structure of DDR3. The inside of DDR3 is a storage array, similar to an excel table, with corresponding rows and columns. We can quickly find the grid we need by numbering the rows and columns. And we also number each table, we call it a storage unit, which is what we often call a logical bank (L-Bank).
And each grid point in the storage unit, we call it a cell. The addresses of the black grid points in the figure below are B1, R6, C5. If the addressing command is B1, R6, C5, then the data stored in this address will be read.
Note: To figure out the relationship between address and data. Think of the memory as a large warehouse, the address is the house number of the small warehouse, and the data is like the goods stored in the warehouse. Addressing is similar to finding the location of data by house number, and reading or writing data is similar to taking the goods out of the warehouse or storing them in.
So what is the amount of data in each cell, which involves the concept of bit width. DDR specifications are generally marked with words such as x4, x8, x16, etc. The number after this x represents the bit width of the DDR chip. They are 4bit, 8bit, and 16bit wide chips. The amount of data stored in each cell in the chip and the bit width are equal, that is to say, for chips of x4, x8, and x16 specifications, the amount of data stored in each cell within them is 4bit, 8bit, and 16bit, respectively.
In addition to logical banks, DDR3 systems also have the concept of physical banks. Also called RANK, for SDRAM devices, the common single Die data bit width is 4Bit (x4), 8Bit (x8) and 16Bit (x16) configurations. For modern 64Bit computers, multiple SDRAMs are needed to splice to complete the required data bit width. For common SDRAM particles with x8 configuration, 8 chips are needed to splice to complete the data bit width of 64Bit. In this way, when the Memory controller addresses a data unit, 8 groups of chips will be selected, so these 8 groups of chips share a Cs_n Signal, we call it 1 RANK.
2. DDR3 capacity calculation and BANK understanding
I think the easiest way to calculate DDR capacity is the number of addresses x bit width, which can also be understood as the number of cells x the amount of data per cell unit.
This picture must have been seen by many people, this is a bit width of 8bit In the DDR3 architecture diagram, there are 14 row address multiplexing lines, 10 column address multiplexing lines, and the number of banks is 8 (2^3). Then the number of addresses of this chip is:
2 to the 14th power × 2 to the 10th power × 2 to the third power = 128M addresses
128M × 8bit = 1Gb
so the amount of data stored by this chip is 1Gbit, and because 8bit = 1B , So 1Gb=128MB. This is what we call a 128MB memory stick every day. Of course, 128Meg×8 has been marked on the top of this picture. This 128Meg means that the chip has 128M addresses (128M cells)
and the bit width is 8, and the capacity can be directly calculated.
There are also some logos such as 16 Meg x 16 x 8 Banks. This 16Meg represents the number of cells in a bank, 16 is 16bit wide, and 8 is the number of banks.
Like the 8-bit wide chip in the figure above, to form a RANK, 8 chips are required to be combined, that is, to form a 1GB memory stick, and the memory size that the CPU can access is 1GB. When the CPU accesses the memory, an address similar to B1, R6, C5 is given. At this time, the CPU thinks that there is only one memory and only one address is given, but the 8 chips that are spliced together will receive this address. The data in the corresponding address will be sent out, each chip will send out 8bit data, and the eight chips will form a RANK with a total of 64 bits.
Three, DDR3 data transmission
1. Prefetch
A major feature of DDR is the prefetch feature. The first generation of DDR is 2-bit prefetch, the second generation is 4-bit prefetch, and the third generation is 8-bit prefetch. Some companies call it 8-n-Prefetch. Technology, 8-bit or 8-n here represents 8 "bits" of data, which means that the amount of data prefetched by the DDR chip each time is 8 × bit wide, such as an 8-bit wide DDR3 chip, then On the rising edge of each DDR internal logic processing clock (this clock frequency is the core frequency of DDR), 64bit data is taken out in parallel. Note that the prefetching method is parallel, and the transmission method is Serial. The data is finally output after a complex parallel-to-serial structure in the middle.
To put it simpler, if the external data bit width is 8bit, DDR3 will read the eight adjacent data at a time according to the 8*8 bit width and then convert and output in parallel, so the internal 100MHz can reach the data rate of 800MHz. In order to achieve a speed-up goal.
2. Transmission rate
Since most of the computer's current RANK is 64-bit, the data transmitted by the memory stick is 64-bit each time. We first call the frequency of the clock pin of the DDR chip the operating frequency, and the DDR transmission method is to transmit once on the rising edge and the falling edge of the clock, so the transmission rate is twice the operating frequency, that is;
every second The number of transmissions = the operating frequency × 2
the amount of data transmitted = the number of transmissions per second × 64bit = the operating frequency × 2 × 64bit
then what is the relationship between the operating frequency and the core frequency, let's take a look at
the above through a simple example Take the 8-bit 128MB chip in the picture above as an example, suppose its core frequency is 100MHz, and the amount of data prefetched each time is 64-bit, but this chip has eight data lines, which means each data line To output 8-bit data in a serial manner within 10ns, since the DDR rising edge and falling edge each transmit 1 bit, then only 4 clocks need to be generated within 10ns, the clock period is 2.5ns, and the frequency is 400MHz , This frequency is the frequency of the clock pin of the DDR chip, which is the operating frequency. It can be seen that:
operating frequency = core frequency × 4
transmission rate = operating frequency × 2 = core frequency × 4 = core frequency × number of prefetches,
then what is the amount of data per second of the memory?
Take the core frequency of 100MHz, bit width 8bit DDR3 For example, eight DDR particles form a memory with a bit width of 64 bits. The amount of data transmitted in this memory each time is 64bit.
Transmission rate=100MHz×8=800M times.
That is to say, the number of data transmissions per second is 800M times, and each transmission is 64bit, then the total data amount is
total data amount=800M×64bit ÷8=6400MBytes=6.4GB It
can be seen that the bandwidth of DDR3 with a core frequency of 100MHz has reached 6.4GB/s. It can be seen that DDR technology has greatly improved the transmission rate.